IEICE TRANSACTIONS on Fundamentals
An Incremental Wiring Algorithm for VLSI Layout Design
Summary :
One of the difficulties in routing problem is in wirability which is to guarantee a physical connection of a given topological route. Wirability often fails since the width of a wire is relatively large compared with the size of modules. As a possible solution, this paper proposes an incremental wiring algorithm which generates wires net-by-net without overlapping other pre-placed circuit elements. The idea is to divide a wire into a series of rectangles and handles them as modules with additional constraints to keep the shape of the wire. The algorithm was implemented and experimented on a small instance to show its promising performance.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.5 pp.1203-1206
- Publication Date
- 2003/05/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Section on Discrete Mathematics and Its Applications)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Yukiko KUBO, Shigetoshi NAKATAKE, Yoji KAJITANI, Masahiro KAWAKITA, "An Incremental Wiring Algorithm for VLSI Layout Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 5, pp. 1203-1206, May 2003, doi: .
Abstract: One of the difficulties in routing problem is in wirability which is to guarantee a physical connection of a given topological route. Wirability often fails since the width of a wire is relatively large compared with the size of modules. As a possible solution, this paper proposes an incremental wiring algorithm which generates wires net-by-net without overlapping other pre-placed circuit elements. The idea is to divide a wire into a series of rectangles and handles them as modules with additional constraints to keep the shape of the wire. The algorithm was implemented and experimented on a small instance to show its promising performance.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_5_1203/_p
Copy
@ARTICLE{e86-a_5_1203,
author={Yukiko KUBO, Shigetoshi NAKATAKE, Yoji KAJITANI, Masahiro KAWAKITA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Incremental Wiring Algorithm for VLSI Layout Design},
year={2003},
volume={E86-A},
number={5},
pages={1203-1206},
abstract={One of the difficulties in routing problem is in wirability which is to guarantee a physical connection of a given topological route. Wirability often fails since the width of a wire is relatively large compared with the size of modules. As a possible solution, this paper proposes an incremental wiring algorithm which generates wires net-by-net without overlapping other pre-placed circuit elements. The idea is to divide a wire into a series of rectangles and handles them as modules with additional constraints to keep the shape of the wire. The algorithm was implemented and experimented on a small instance to show its promising performance.},
keywords={},
doi={},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - An Incremental Wiring Algorithm for VLSI Layout Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1203
EP - 1206
AU - Yukiko KUBO
AU - Shigetoshi NAKATAKE
AU - Yoji KAJITANI
AU - Masahiro KAWAKITA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2003
AB - One of the difficulties in routing problem is in wirability which is to guarantee a physical connection of a given topological route. Wirability often fails since the width of a wire is relatively large compared with the size of modules. As a possible solution, this paper proposes an incremental wiring algorithm which generates wires net-by-net without overlapping other pre-placed circuit elements. The idea is to divide a wire into a series of rectangles and handles them as modules with additional constraints to keep the shape of the wire. The algorithm was implemented and experimented on a small instance to show its promising performance.
ER -
English
