A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications

Jinjia ZHOU; Dajiang ZHOU; Xun HE; Satoshi GOTO

doi:10.1587/transfun.E93.A.1425

A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications

Jinjia ZHOU, Dajiang ZHOU, Xun HE, Satoshi GOTO

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In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 38402160@60 fps decoding at less than 133 MHz, with 37.2 k logic gates. Meanwhile, by applying the proposed scheme, 85-98% bandwidth saving is achieved, compared with storing the original information for every 44 block to DRAM.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.8 pp.1425-1433

Publication Date: 2010/08/01

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Online ISSN: 1745-1337

DOI: 10.1587/transfun.E93.A.1425

Type of Manuscript: Special Section PAPER (Special Section on Signal Processing)

Category: VLSI Design Technology and CAD

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Jinjia ZHOU, Dajiang ZHOU, Xun HE, Satoshi GOTO, "A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications" in IEICE TRANSACTIONS on Fundamentals, vol. E93-A, no. 8, pp. 1425-1433, August 2010, doi: 10.1587/transfun.E93.A.1425.
Abstract: In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 38402160@60 fps decoding at less than 133 MHz, with 37.2 k logic gates. Meanwhile, by applying the proposed scheme, 85-98% bandwidth saving is achieved, compared with storing the original information for every 44 block to DRAM.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.1425/_p

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@ARTICLE{e93-a_8_1425,
author={Jinjia ZHOU, Dajiang ZHOU, Xun HE, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications},
year={2010},
volume={E93-A},
number={8},
pages={1425-1433},
abstract={In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 38402160@60 fps decoding at less than 133 MHz, with 37.2 k logic gates. Meanwhile, by applying the proposed scheme, 85-98% bandwidth saving is achieved, compared with storing the original information for every 44 block to DRAM.},
keywords={},
doi={10.1587/transfun.E93.A.1425},
ISSN={1745-1337},
month={August},}

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TY - JOUR
TI - A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1425
EP - 1433
AU - Jinjia ZHOU
AU - Dajiang ZHOU
AU - Xun HE
AU - Satoshi GOTO
PY - 2010
DO - 10.1587/transfun.E93.A.1425
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2010
AB - In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 38402160@60 fps decoding at less than 133 MHz, with 37.2 k logic gates. Meanwhile, by applying the proposed scheme, 85-98% bandwidth saving is achieved, compared with storing the original information for every 44 block to DRAM.
ER -