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[Author] Yasuhiko ISHIKAWA(2hit)

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  • Effect of Post-Growth Annealing on Morphology of Ge Mesa Selectively Grown on Si

    Sungbong PARK  Yasuhiko ISHIKAWA  Tai TSUCHIZAWA  Toshifumi WATANABE  Koji YAMADA  Sei-ichi ITABASHI  Kazumi WADA  

     
    PAPER

      Vol:
    E91-C No:2
      Page(s):
    181-186

    Effect of the post-growth annealing on the morphology of a Ge mesa selectively grown on Si was studied from the viewpoint of near-infrared photodiode applications. By ultrahigh-vacuum chemical vapor deposition, Ge mesas were selectively grown at 600 on Si (001) substrates partially covered with SiO2 masks. The as-grown Ge mesas showed trapezoidal cross-sections having a top (001) surface and {311} sidewall facets, as similar to previous reports. However, after the subsequent post-growth annealing at ~800 in the ultrahigh-vacuum chamber, the mesas were deformed into rounded shapes having a depression at the center and mounds near the edges. Such a deformation cannot be observed for the samples annealed once after cooled and exposed to the air. The residual hydrogen atoms on the Ge surface from the germane (GeH4) decomposition is regarded as a trigger to the observed morphological instability, while the final mesa shape is determined in order to minimize a sum of the surface and/or strain energies.

  • Reduced Peripheral Leakage Current in Pin Photodetectors of Ge on n+-Si by P+ Implantation to Compensate Surface Holes Open Access

    Koji ABE  Mikiya KUZUTANI  Satoki FURUYA  Jose A. PIEDRA-LORENZANA  Takeshi HIZAWA  Yasuhiko ISHIKAWA  

     
    BRIEF PAPER

      Pubricized:
    2024/05/15
      Vol:
    E107-C No:9
      Page(s):
    237-240

    A reduced dark leakage current, without degrading the near-infrared responsivity, is reported for a vertical pin structure of Ge photodiodes (PDs) on n+-Si substrate, which usually shows a leakage current higher than PDs on p+-Si. The peripheral/surface leakage, the dominant leakage in PDs on n+-Si, is significantly suppressed by globally implanting P+ in the i-Si cap layer protecting the fragile surface of i-Ge epitaxial layer before locally implanting B+/BF2+ for the top p+ region of the pin junction. The P+ implantation compensates free holes unintentionally induced due to the Fermi level pinning at the surface/interface of Ge. By preventing the hole conduction from the periphery to the top p+ region under a negative/reverse bias, a reduction in the leakage current of PDs on n+-Si is realized.