A reduced dark leakage current, without degrading the near-infrared responsivity, is reported for a vertical pin structure of Ge photodiodes (PDs) on n+-Si substrate, which usually shows a leakage current higher than PDs on p+-Si. The peripheral/surface leakage, the dominant leakage in PDs on n+-Si, is significantly suppressed by globally implanting P+ in the i-Si cap layer protecting the fragile surface of i-Ge epitaxial layer before locally implanting B+/BF2+ for the top p+ region of the pin junction. The P+ implantation compensates free holes unintentionally induced due to the Fermi level pinning at the surface/interface of Ge. By preventing the hole conduction from the periphery to the top p+ region under a negative/reverse bias, a reduction in the leakage current of PDs on n+-Si is realized.