Low Power 8-b CMOS Current Steering Folding-Interpolating A/D Converter

Do Danh CUONG; Zhi-Yuan CUI; Nam-Soo KIM; Kie-Yong LEE; Ho-Yong CHOI

doi:10.1093/ietele/e91-c.1.81

Low Power 8-b CMOS Current Steering Folding-Interpolating A/D Converter

Do Danh CUONG, Zhi-Yuan CUI, Nam-Soo KIM, Kie-Yong LEE, Ho-Yong CHOI

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This paper presents a CMOS A/D converter based on the folding and interpolating technique. A current steering folder composed of differential pairs allows low power operation and an interpolation is used for high speed with low supply voltage. In a folding circuit, only twenty-three MOSFETs are required to have eight reference voltages of an 8-b A/D converter. The interpolation is implemented with a current division technique to generate 32 folding signals. This approach requires much less area and power consumption than other conventional flash A/D converter. The simulation in a 0.35 µm CMOS process achieves 8-b resolution at 250 Msample/s with power consumption 70 mW at 3.3 V power supply. The preliminary experiment indicates the current steering folder and coarse bits operate as expected.

Publication: IEICE TRANSACTIONS on Electronics Vol.E91-C No.1 pp.81-86

Publication Date: 2008/01/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e91-c.1.81

Type of Manuscript: PAPER

Category: Electronic Circuits

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Do Danh CUONG, Zhi-Yuan CUI, Nam-Soo KIM, Kie-Yong LEE, Ho-Yong CHOI, "Low Power 8-b CMOS Current Steering Folding-Interpolating A/D Converter" in IEICE TRANSACTIONS on Electronics, vol. E91-C, no. 1, pp. 81-86, January 2008, doi: 10.1093/ietele/e91-c.1.81.
Abstract: This paper presents a CMOS A/D converter based on the folding and interpolating technique. A current steering folder composed of differential pairs allows low power operation and an interpolation is used for high speed with low supply voltage. In a folding circuit, only twenty-three MOSFETs are required to have eight reference voltages of an 8-b A/D converter. The interpolation is implemented with a current division technique to generate 32 folding signals. This approach requires much less area and power consumption than other conventional flash A/D converter. The simulation in a 0.35 µm CMOS process achieves 8-b resolution at 250 Msample/s with power consumption 70 mW at 3.3 V power supply. The preliminary experiment indicates the current steering folder and coarse bits operate as expected.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.1.81/_p

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@ARTICLE{e91-c_1_81,
author={Do Danh CUONG, Zhi-Yuan CUI, Nam-Soo KIM, Kie-Yong LEE, Ho-Yong CHOI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low Power 8-b CMOS Current Steering Folding-Interpolating A/D Converter},
year={2008},
volume={E91-C},
number={1},
pages={81-86},
abstract={This paper presents a CMOS A/D converter based on the folding and interpolating technique. A current steering folder composed of differential pairs allows low power operation and an interpolation is used for high speed with low supply voltage. In a folding circuit, only twenty-three MOSFETs are required to have eight reference voltages of an 8-b A/D converter. The interpolation is implemented with a current division technique to generate 32 folding signals. This approach requires much less area and power consumption than other conventional flash A/D converter. The simulation in a 0.35 µm CMOS process achieves 8-b resolution at 250 Msample/s with power consumption 70 mW at 3.3 V power supply. The preliminary experiment indicates the current steering folder and coarse bits operate as expected.},
keywords={},
doi={10.1093/ietele/e91-c.1.81},
ISSN={1745-1353},
month={January},}

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TY - JOUR
TI - Low Power 8-b CMOS Current Steering Folding-Interpolating A/D Converter
T2 - IEICE TRANSACTIONS on Electronics
SP - 81
EP - 86
AU - Do Danh CUONG
AU - Zhi-Yuan CUI
AU - Nam-Soo KIM
AU - Kie-Yong LEE
AU - Ho-Yong CHOI
PY - 2008
DO - 10.1093/ietele/e91-c.1.81
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2008
AB - This paper presents a CMOS A/D converter based on the folding and interpolating technique. A current steering folder composed of differential pairs allows low power operation and an interpolation is used for high speed with low supply voltage. In a folding circuit, only twenty-three MOSFETs are required to have eight reference voltages of an 8-b A/D converter. The interpolation is implemented with a current division technique to generate 32 folding signals. This approach requires much less area and power consumption than other conventional flash A/D converter. The simulation in a 0.35 µm CMOS process achieves 8-b resolution at 250 Msample/s with power consumption 70 mW at 3.3 V power supply. The preliminary experiment indicates the current steering folder and coarse bits operate as expected.
ER -