In this paper, an improved charge pump (CP) and a modified nonlinear phase frequency detector (PFD) are designed and fabricated in a 90-nm CMOS process. The CP is optimized with a combination of circuit techniques such as pedestal error cancel scheme to eliminate the charge injection and the other non-ideal characteristics. The nonlinear PFD is based on a modified circuit topology to enhance the acquisition capability of the PLL. The optimized CP and nonlinear PFD are integrated into a Ka-band PLL. The measured output current mismatch ratio of the improved CP is less than 1% when the output voltage Vout fluctuates between 0.2 to 1.1V from a 1.2V power supply. The measured phase error detection range of the modified nonlinear PFD is between -2π and 2π. Owing to the modified CP and PFD, the measured reference spur of the Ka-band PLL frequency synthesizer containing the optimized CP and PFD is only -56.409dBc at 30-GHz at the locked state.

We report good responsivity at the wavelength of 1600nm in a Ge photodetector which had lateral p-i-n structure and butt-joint coupling structure based on conventional normal complementary metal oxide semiconductor processes. We experimentally verified the responsivity of 0.82A/W and 0.71A/W on the best and the worst polarizations, respectively. The butt joint lateral p-i-n structure is found to be polarization independent as compared with vertical ones. Although cut-off frequency was 2.3-2.4GHz at reverse bias 3V, clearly open eye diagram at 10Gbps was obtained with reverse bias over 12V. These results are promising as optical photodetectors to receive long wavelengths downstream signal wavelengths required for next-generation optical access network systems.

nMOS-type and pMOS-type silicon avalanche photodiodes (APDs) were fabricated by standard 0.18µm CMOS process, and the current-voltage characteristic and the frequency response of the APDs with and without guard ring structure were measured. The role of the guard ring is cancellation of photo-generated carriers in a deep layer and a substrate. The bandwidth of the APD is enhanced with the guard ring structure at a sacrifice of the responsivity. Based on comparison of nMOS-type and pMOS-type APDs, the nMOS-type APD is more suitable for high-speed operation. The bandwidth is enhanced with decreasing the spacing of interdigital electrodes due to decreased carrier transit time and with decreasing the detection area and the PAD size for RF probing due to decreased device capacitance. The maximum bandwidth was achieved with the avalanche gain of about 10. Finally, we fabricated a nMOS-type APD with the electrode spacing of 0.84µm, the detection area of 10×10µm2, the PAD size for RF probing of 30×30µm2, and with the guard ring structure. The maximum bandwidth of 8.4GHz was achieved along with the gain-bandwidth product of 280GHz.

This paper presents a wideband differential amplifier operating at 141GHz in 40-nm CMOS. It is composed of five differential common source stages with cross-coupled capacitors. A small-signal gain of 20dB and a 3-dB bandwidth of 22GHz are achieved. It consumes 75mW from a 0.94-V voltage supply. The die area with balun and pads is 945×842µm2 and the size of the core not including input/output matching networks is 201×284µm2. The small core area is made possible by using a refined “fishbone” layout technique.

The paper demonstrates a novel multiple-valued logic (MVL) design using a three-peak negative differential resistance (NDR) circuit, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT) devices. Specifically, this three-peak NDR circuit is biased by two switch-controlled current sources. Compared to the traditional MVL circuit made of resonant tunneling diode (RTD), this multiple-peak MOS-HBT-NDR circuit has two major advantages. One is that the fabrication of this circuit can be fully implemented by the standard BiCMOS process without the need for molecular-beam epitaxy system. Another is that we can obtain more logic states than the RTD-based MVL design. In measuring, we can obtain eight logic states at the output according to a sequent control of two current sources on and off in order.

A multiple-peak negative differential resistance (NDR) circuit made of standard Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT) is demonstrated. We can obtain a three-peak I-V curve by connecting three cascoded MOS-HBT-NDR circuits by suitably designing the MOS parameters. This novel three-peak NDR circuit possesses the adjustable current-voltage characteristics and high peak-to-valley current ratio (PVCR). We can adjust the PVCR values to be as high as 11.5, 6.5, and 10.3 for three peaks, respectively. Because the NDR circuit is a very strong nonlinear element, we discuss the extrinsic hysteresis phenomena in this multiple-peak NDR circuit. The effect of series resistance on hysteresis phenomena is also investigated. Our design and fabrication of the NDR circuit is based on the standard 0.35 µm SiGe BiCMOS process.

This paper introduces a new folding amplifier in a folding and interpolating 10-b ADC. The amplifier consists of current mirrors and differential stages. Only one current source is exploited in cascaded differential pairs, which reduces the power consumption significantly. In the folding circuit, the interpolation is implemented with a current division technique. An experiment of the amplifier in 10-b folding signal has been integrated in a single-poly four-metal 0.35 µm CMOS process. The simulation in 10-b folding ADC shows that power consumption is 225 mW at the sampling speed of 250 Msample/s and the power supply of 3.3 V. The preliminary experiment indicates the current steering folder and digital bits operate as expected.

A silicon lateral photodiode is fabricated by standard 0.18 µm CMOS process, and the optical detection property is characterized. The photodiode has interdigital electrode structure with the electrode width of 0.22 µm and the electrode spacing of 0.6 µm. At 830 nm wavelength, the responsivity is 0.12 A/W at low bias voltage, and is increased to 0.6 A/W due to avalanche amplification. The bandwidth is also enhanced from 12 MHz at low bias voltage to 100 MHz at the bias voltage close to the breakdown voltage.

This paper presents a CMOS A/D converter based on the folding and interpolating technique. A current steering folder composed of differential pairs allows low power operation and an interpolation is used for high speed with low supply voltage. In a folding circuit, only twenty-three MOSFETs are required to have eight reference voltages of an 8-b A/D converter. The interpolation is implemented with a current division technique to generate 32 folding signals. This approach requires much less area and power consumption than other conventional flash A/D converter. The simulation in a 0.35 µm CMOS process achieves 8-b resolution at 250 Msample/s with power consumption 70 mW at 3.3 V power supply. The preliminary experiment indicates the current steering folder and coarse bits operate as expected.

A 1-V operational sigma-delta modulator with a second-order passive switched capacitor filter is designed and fabricated by using a 90 nm CMOS process. No gate-voltage bootstrapped scheme is adopted to drive analog switches, and the voltage gain of a comparator is chosen to be 94 dB. The experimental results show that the peak SNR reached 68.9 dB with a frequency bandwidth of 40 kHz when the clock was 40 MHz.

Based on the Si CMOS process, a low operating voltage and low power light emitting device is presented. It has a power transfer efficiency of 1 to 2 orders higher than previous reports and can be used as a high efficiency photodiode. Configurations using the same structure as both the light emitter and the optical receiver, and employing a simple modulation instrument is then proposed for applications in the chip-to-chip optical alignment and the signal transmission. Only single power supply is required in the emitter-receiver circuits and is compatible with other integrated circuits made by the CMOS process.

A novel double-image Green's function approach is proposed to compute the frequency- dependent capacitance and conductance for the general CMOS oriented transmission lines with one protective layer. The ε-algorithm of Pade approximation is adopted to reduce the time for establishing coefficient matrix in this letter. The parameters gained from this new approach are shown to be in good agreement with the data obtained by the full-wave method and the total charge Green's function method.

This paper describes the robust design of the 30 V high voltage NMOS (HVNMOS) structure implemented in a 0.6 µm 5 V standard CMOS processes without any additional masks or process steps. The structure makes use of the field oxide (FOX) and light doping N-well to increase the drain to gate and drain to bulk breakdown voltages, respectively. By varying the six spacing parameters: the channel length, gate overlap FOX, N-well overlap channel length, poly to the active area of the drain (OD2), metal extend beyond the OD2 and N-well extend beyond the OD2 in HVNMOS structure, the breakdown voltage can be improved. The experimental results show that the breakdown voltage of the normal NMOS is 11 V, and the breakdown voltage of the HVNMOS is increased to over 30 V. With the optimized layout parameters of the HVNMOS, it can be increased to 38 V.

In this paper, we present a 10 Gbase Ethernet Transceiver that is suitable for 10 Gb/s Ethernet applications. The 10 Gbase Ethernet Transceiver LSI, which contains the high-speed interface and the fully integrated IEEE 802.3ae compliant logics, is fabricated in a 0.18 µm SOI/CMOS process and dissipates 2.9 W at 1.8 V supply. By incorporating the monolithic approach and the use of the advance CMOS process, this 10 GbE transceiver realizes a low power, low cost and compact solution for the exponentially increasing need of broadband network applications.

In this paper, a new design idea for class A CMOS second generation current conveyor (CCII) is discussed. Based on the proposed idea, a new architecture for a CMOS CCII is presented. The proposed circuit is free from body effect and provides high performance in terms of input resistance and transfer gain errors. HSPICE simulation results also have shown remarkable performance over the wide bandwidth.