Low Power 10-b 250 Msample/s CMOS Cascaded Folding and Interpolating A/D Converter
Summary :
This paper introduces a new folding amplifier in a folding and interpolating 10-b ADC. The amplifier consists of current mirrors and differential stages. Only one current source is exploited in cascaded differential pairs, which reduces the power consumption significantly. In the folding circuit, the interpolation is implemented with a current division technique. An experiment of the amplifier in 10-b folding signal has been integrated in a single-poly four-metal 0.35 µm CMOS process. The simulation in 10-b folding ADC shows that power consumption is 225 mW at the sampling speed of 250 Msample/s and the power supply of 3.3 V. The preliminary experiment indicates the current steering folder and digital bits operate as expected.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E92-C No.8 pp.1073-1079
- Publication Date
- 2009/08/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E92.C.1073
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Zhi-Yuan CUI, Yong-Gao JIN, Nam-Soo KIM, Ho-Yong CHOI, "Low Power 10-b 250 Msample/s CMOS Cascaded Folding and Interpolating A/D Converter" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 8, pp. 1073-1079, August 2009, doi: 10.1587/transele.E92.C.1073.
Abstract: This paper introduces a new folding amplifier in a folding and interpolating 10-b ADC. The amplifier consists of current mirrors and differential stages. Only one current source is exploited in cascaded differential pairs, which reduces the power consumption significantly. In the folding circuit, the interpolation is implemented with a current division technique. An experiment of the amplifier in 10-b folding signal has been integrated in a single-poly four-metal 0.35 µm CMOS process. The simulation in 10-b folding ADC shows that power consumption is 225 mW at the sampling speed of 250 Msample/s and the power supply of 3.3 V. The preliminary experiment indicates the current steering folder and digital bits operate as expected.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1073/_p
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@ARTICLE{e92-c_8_1073,
author={Zhi-Yuan CUI, Yong-Gao JIN, Nam-Soo KIM, Ho-Yong CHOI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low Power 10-b 250 Msample/s CMOS Cascaded Folding and Interpolating A/D Converter},
year={2009},
volume={E92-C},
number={8},
pages={1073-1079},
abstract={This paper introduces a new folding amplifier in a folding and interpolating 10-b ADC. The amplifier consists of current mirrors and differential stages. Only one current source is exploited in cascaded differential pairs, which reduces the power consumption significantly. In the folding circuit, the interpolation is implemented with a current division technique. An experiment of the amplifier in 10-b folding signal has been integrated in a single-poly four-metal 0.35 µm CMOS process. The simulation in 10-b folding ADC shows that power consumption is 225 mW at the sampling speed of 250 Msample/s and the power supply of 3.3 V. The preliminary experiment indicates the current steering folder and digital bits operate as expected.},
keywords={},
doi={10.1587/transele.E92.C.1073},
ISSN={1745-1353},
month={August},}
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TY - JOUR
TI - Low Power 10-b 250 Msample/s CMOS Cascaded Folding and Interpolating A/D Converter
T2 - IEICE TRANSACTIONS on Electronics
SP - 1073
EP - 1079
AU - Zhi-Yuan CUI
AU - Yong-Gao JIN
AU - Nam-Soo KIM
AU - Ho-Yong CHOI
PY - 2009
DO - 10.1587/transele.E92.C.1073
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2009
AB - This paper introduces a new folding amplifier in a folding and interpolating 10-b ADC. The amplifier consists of current mirrors and differential stages. Only one current source is exploited in cascaded differential pairs, which reduces the power consumption significantly. In the folding circuit, the interpolation is implemented with a current division technique. An experiment of the amplifier in 10-b folding signal has been integrated in a single-poly four-metal 0.35 µm CMOS process. The simulation in 10-b folding ADC shows that power consumption is 225 mW at the sampling speed of 250 Msample/s and the power supply of 3.3 V. The preliminary experiment indicates the current steering folder and digital bits operate as expected.
ER -
English
