IEICE TRANSACTIONS on Electronics
A 30 V High Voltage NMOS Structure Design in Standard 5 V CMOS Processes
Summary :
This paper describes the robust design of the 30 V high voltage NMOS (HVNMOS) structure implemented in a 0.6 µm 5 V standard CMOS processes without any additional masks or process steps. The structure makes use of the field oxide (FOX) and light doping N-well to increase the drain to gate and drain to bulk breakdown voltages, respectively. By varying the six spacing parameters: the channel length, gate overlap FOX, N-well overlap channel length, poly to the active area of the drain (OD2), metal extend beyond the OD2 and N-well extend beyond the OD2 in HVNMOS structure, the breakdown voltage can be improved. The experimental results show that the breakdown voltage of the normal NMOS is 11 V, and the breakdown voltage of the HVNMOS is increased to over 30 V. With the optimized layout parameters of the HVNMOS, it can be increased to 38 V.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E86-C No.11 pp.2341-2345
- Publication Date
- 2003/11/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- Semiconductor Materials and Devices
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Tzu-Chao LIN, Jiin-Chuan WU, "A 30 V High Voltage NMOS Structure Design in Standard 5 V CMOS Processes" in IEICE TRANSACTIONS on Electronics,
vol. E86-C, no. 11, pp. 2341-2345, November 2003, doi: .
Abstract: This paper describes the robust design of the 30 V high voltage NMOS (HVNMOS) structure implemented in a 0.6 µm 5 V standard CMOS processes without any additional masks or process steps. The structure makes use of the field oxide (FOX) and light doping N-well to increase the drain to gate and drain to bulk breakdown voltages, respectively. By varying the six spacing parameters: the channel length, gate overlap FOX, N-well overlap channel length, poly to the active area of the drain (OD2), metal extend beyond the OD2 and N-well extend beyond the OD2 in HVNMOS structure, the breakdown voltage can be improved. The experimental results show that the breakdown voltage of the normal NMOS is 11 V, and the breakdown voltage of the HVNMOS is increased to over 30 V. With the optimized layout parameters of the HVNMOS, it can be increased to 38 V.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e86-c_11_2341/_p
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@ARTICLE{e86-c_11_2341,
author={Tzu-Chao LIN, Jiin-Chuan WU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 30 V High Voltage NMOS Structure Design in Standard 5 V CMOS Processes},
year={2003},
volume={E86-C},
number={11},
pages={2341-2345},
abstract={This paper describes the robust design of the 30 V high voltage NMOS (HVNMOS) structure implemented in a 0.6 µm 5 V standard CMOS processes without any additional masks or process steps. The structure makes use of the field oxide (FOX) and light doping N-well to increase the drain to gate and drain to bulk breakdown voltages, respectively. By varying the six spacing parameters: the channel length, gate overlap FOX, N-well overlap channel length, poly to the active area of the drain (OD2), metal extend beyond the OD2 and N-well extend beyond the OD2 in HVNMOS structure, the breakdown voltage can be improved. The experimental results show that the breakdown voltage of the normal NMOS is 11 V, and the breakdown voltage of the HVNMOS is increased to over 30 V. With the optimized layout parameters of the HVNMOS, it can be increased to 38 V.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A 30 V High Voltage NMOS Structure Design in Standard 5 V CMOS Processes
T2 - IEICE TRANSACTIONS on Electronics
SP - 2341
EP - 2345
AU - Tzu-Chao LIN
AU - Jiin-Chuan WU
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2003
AB - This paper describes the robust design of the 30 V high voltage NMOS (HVNMOS) structure implemented in a 0.6 µm 5 V standard CMOS processes without any additional masks or process steps. The structure makes use of the field oxide (FOX) and light doping N-well to increase the drain to gate and drain to bulk breakdown voltages, respectively. By varying the six spacing parameters: the channel length, gate overlap FOX, N-well overlap channel length, poly to the active area of the drain (OD2), metal extend beyond the OD2 and N-well extend beyond the OD2 in HVNMOS structure, the breakdown voltage can be improved. The experimental results show that the breakdown voltage of the normal NMOS is 11 V, and the breakdown voltage of the HVNMOS is increased to over 30 V. With the optimized layout parameters of the HVNMOS, it can be increased to 38 V.
ER -
English
