This paper reports the new gate and recess structure design of millimeter-wave, high power pHEMTs, which highly improves humidity resistance and reliability. By using tantalum nitride as the refractory gate metal and a silicon nitride layer prepared by a catalytic chemical vapor deposition technique for passivation of this transistor, strong moisture resistance was obtained without degradation of the device characteristics. Moreover, we have designed a stepped recess structure to increase the on-state breakdown voltage without degradation of the power density of the millimeter-wave pHEMT, according to the analysis based on the new nonlinear drain resistance model. Consequently, the developed pHEMT has shown strong humidity resistance with no degradation of the DC characteristics even after 1000 hours storage at 400 K and 85% humidity, and the high on-state breakdown voltage of over 30 V while keeping the high power density of 0.65 W/mm in the Ka band. In addition, the proposed nonlinear drain resistance model effectively explains this power performance.

The linear operation of a HBT with a GaAs/InGaP composite collector structure is demonstrated. The composite collector structure allows for a thin collector design that is suitable for the linear operation of a HBT without critical degradation of the breakdown voltage. The load pull measurements under a 1.95 GHz WCDMA signal have shown that a composite-collector HBT with a 400-nm thick collector layer operates with power-added-efficiency (PAE) as high as 53% at VCE = 3.5 V as a result of improved distortion characteristics. Despite the thin collector design, collector-emitter breakdown voltage of 11 V was achieved even at current density of 10 kA/cm2. The composite-collector HBT has even greater advantage for future low voltage (< 3 V) applications where maintaining PAE and linearity becomes one of the critical issues.

This paper describes the robust design of the 30 V high voltage NMOS (HVNMOS) structure implemented in a 0.6 µm 5 V standard CMOS processes without any additional masks or process steps. The structure makes use of the field oxide (FOX) and light doping N-well to increase the drain to gate and drain to bulk breakdown voltages, respectively. By varying the six spacing parameters: the channel length, gate overlap FOX, N-well overlap channel length, poly to the active area of the drain (OD2), metal extend beyond the OD2 and N-well extend beyond the OD2 in HVNMOS structure, the breakdown voltage can be improved. The experimental results show that the breakdown voltage of the normal NMOS is 11 V, and the breakdown voltage of the HVNMOS is increased to over 30 V. With the optimized layout parameters of the HVNMOS, it can be increased to 38 V.

We demonstrated the uniformity and stability as well as the high breakdown voltage of 0.1-µm-gate InP HEMTs with a double recess structure. To overcome the drawbacks regarding the uniformity and stability in the double recess structure, an InP passivation layer that functions as an etch-stopper and a surface passivator was successfully applied to the structure. It was confirmed that there was no degradation in the uniformity and stability of device performance for the double recess HEMTs that had the breakdown voltages in the on-state and off-state improved by a factor of 1.6.

DC and RF performances of AlGaN/GaN HEMTs are simulated using a two-dimensional device simulator with the material parameters of GaN and AlGaN. The cut-off frequency is estimated as 205 GHz at the gate length of 0.05 µm and the drain breakdown voltage at this gate length is over 10 V. The values are satisfactory for millimeter wavelength power applications. The use of thin AlGaN layers has key importance to alleviate gate parasitic capacitance effects at this gate length.

We have developed InGaP-channel field effect transistors (FETs) with high breakdown voltages that can be fabricated by using conventional GaAs FET fabrication processes. The buffer and barrier layers were also optimized for the realization of high-voltage operation. The InGaP-channel FET has an extremely high on-state drain-to-source breakdown voltage of over 40 V, and a gate-to-drain breakdown voltage of 55 V. This enabled high-voltage large-signal operation at 40 V. The third-order intermodulation distortion of the InGaP channel FETs was 10-20 dB lower than that of an equivalent GaAs-channel FET, due to the high operating voltage.

The subject of this study is to propose a new structure that can realize simultaneously high breakdown voltage and high packing density for both Nch low side switch and Pch high side switch in 200 V class rating. As the conventional techniques for the electric field relaxation, the structure of field plate, field ring and RESURF are well known, but these techniques are inadequate for the high packing density because they are the techniques in surface region. In order to conquer this subject, it is necessary to relax the electric field in the deep region. The electric field relaxation was investigated by device simulation. In the Nch low side switch the electric field is relaxed by buried oxide film in SOI structure. However, electric field relaxation cannot be realized only by adapting the SOI structure for Pch high side switch. Then we tried to insert an intrinsic layer between P-drift layer and the buried oxide film in order to spread the depletion layer in the deep region. This spread depletion layer by intrinsic layer and the depletion layer by field plate connect vertically, and the dosage of the ion implantation for drift layer can be set to two times higher than the case without intrinsic layer. As the results, it was revealed that the SOI structure with intrinsic layer is effective to achieve this subject. Furthermore, by fabricating both Nch low side switch and Pch high side switch on intrinsic SOI substrate, breakdown voltage more than 250 V were achieved.

A buried gate AlGaAs/InGaAs heterojunction FET (HJFET) with gate breakdown voltage of 30 V was examined for high drain bias (higher than 10 V) operation. High breakdown voltage was realized due to the optimization of the narrow recess depth. A 1.4 mm HJFET has exhibited an output power of 30.2 dBm (1050 mW) with 50% power added efficiency (PAE) and 12.1 dB linear gain at 12 GHz with a 13 V drain bias. An internal matching circuit for a 16.8 mm HJFET was designed using a large-signal load impedance determined from load-pull measurement. The 16.8 mm internally-matched HJFET has delivered 38.9 dBm (7.8 W) output power with 46% PAE and 11.6 dB linear gain at 12 GHz with a drain bias of 13 V. This is the first report of higher than 10 V operation of an X- and Ku-band power HJFET with the excellent power performance.