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In this paper, we propose a novel coding scheme for the geometry of the triangular mesh model. The geometry coding schemes can be classified into two groups: schemes with perfect reconstruction property that maintains their connectivity, and schemes without it in which the remeshing procedure is performed to change the mesh to semi-regular or regular mesh. The former schemes have good coding performance at higher coding rate, while the latter give excellent coding performance at lower coding rate. We propose a geometry coding scheme that maintains the connectivity and has a perfect reconstruction property. We apply a method that successively structures on 2-D plane the surrounding vertices obtained by expanding vertex sequences neighboring the previous layer. Non-separable component decomposition is applied, in which 2-D structured data are decomposed into four components depending on whether their location was even or odd on the horizontal and vertical axes in the 2-D plane. And a prediction and update are performed for the decomposed components. In the prediction process the predicted value is obtained from the vertices, which were not processed, neighboring the target vertex in the 3-D space. And the zero-tree coding is introduced in order to remove the redundancies between the coefficients at similar positions in different resolution levels. SFQ (Space-Frequency Quantization) is applied, which gives the optimal combination of coefficient pruning for the descendant coefficients of each tree element and a uniform quantization for each coefficient. Experiments applying the proposed method to several polygon meshes of different resolutions show that the proposed method gives a better coding performance at lower bit rate when compared to the conventional schemes.
This paper presents a lifting wavelet coding technique with permutation and coefficient modification processes for coding the structured geometry data of 3-D polygonal mesh model. One promising method for coding 3-D geometry data is based on the structure processing of a 3-D model on a triangle lattice plane, while maintaining connectivity. In the structuring process, each vertex may be assigned to several nodes on the triangular lattice plane. One of the nodes to which a vertex is assigned is selected as a representative node and the others are called expanded nodes. Only the geometry data of the vertices at the representative nodes are required for reconstructing the 3-D model. In this paper we apply a lifting wavelet transform with a permutation process for an expanded node at an even location in each decomposition step and the neighboring representative node. This scheme arranges more representative nodes into the lower frequency band. Also many representative nodes separated from the connective expanded nodes are made to adjoin each other in lower frequency bands, and the correlation between the representative nodes will be reduced by the following decomposition process. A process is added to use the modified coefficients obtained from the coefficients of the adjacent representative nodes instead of the original coefficients in the permutation process. This has the effect of restraining increases in the decomposed coefficients with larger magnitude. Some experiments in which the proposed scheme was applied to structured geometry data of a 3-D model with complex connectivity show that the proposed scheme gives better coding performance and the reconstructed models are more faithful to the original in comparison with the usual schemes.
Chikau TAKAHASHI Ryuichi FUJIMOTO Satoshi ARAI Tetsuro ITAKURA Takashi UENO Hiroshi TSURUMI Hiroshi TANIMOTO Shuji WATANABE Kenji HIRAKAWA
A 1.9GHz direct conversion receiver(DCR) chip which integrates an LNA, I/Q mixers(MIX), active lowpass filters(LDF) and variable gain amplifiers(VGA) was fabricated. Because the DCR for QPSK modulation systems is sensitive to the 2nd-order nonlinearity, linearization techniques are adopted in MIX and LPF. The DCR chip was fabricated using a BiCMOS process, and the die size is 5.1 mm by 5.1mm. The chip can operate from 2.7 V supply voltage and consumes 165mW when all the functions are activated. Suppression of local signal radiation and the 2nd-order distortion indicate the feasibility of Si-based DCR for QPSK modulation systems such as PHS.