IEICE TRANSACTIONS on Communications
Broadband and Flexible Receiver Architecture for Software Defined Radio Terminal Using Direct Conversion and Low-IF Principle
Summary :
A broadband and flexible receiver architecture is investigated for the handheld software defined radio (SDR). The proposed SDR architecture is based on the direct conversion and low intermediate frequency (low-IF) principle with digital channel filtering, which provides the receiver with flexibility for the multi-standard application. This architecture also enables analog-to-digital converter activating essentially in baseband or low frequency so that the clock jitter, which serves as an important subject in the well-known IF sampling method, can be reduced. Basic performance of the proposed architecture has been confirmed by the experimental model.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E83-B No.6 pp.1246-1253
- Publication Date
- 2000/06/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Software Defined Radio and Its Technologies)
- Category
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Hiroshi TSURUMI, Hiroshi YOSHIDA, Shoji OTAKA, Hiroshi TANIMOTO, Yasuo SUZUKI, "Broadband and Flexible Receiver Architecture for Software Defined Radio Terminal Using Direct Conversion and Low-IF Principle" in IEICE TRANSACTIONS on Communications,
vol. E83-B, no. 6, pp. 1246-1253, June 2000, doi: .
Abstract: A broadband and flexible receiver architecture is investigated for the handheld software defined radio (SDR). The proposed SDR architecture is based on the direct conversion and low intermediate frequency (low-IF) principle with digital channel filtering, which provides the receiver with flexibility for the multi-standard application. This architecture also enables analog-to-digital converter activating essentially in baseband or low frequency so that the clock jitter, which serves as an important subject in the well-known IF sampling method, can be reduced. Basic performance of the proposed architecture has been confirmed by the experimental model.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e83-b_6_1246/_p
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@ARTICLE{e83-b_6_1246,
author={Hiroshi TSURUMI, Hiroshi YOSHIDA, Shoji OTAKA, Hiroshi TANIMOTO, Yasuo SUZUKI, },
journal={IEICE TRANSACTIONS on Communications},
title={Broadband and Flexible Receiver Architecture for Software Defined Radio Terminal Using Direct Conversion and Low-IF Principle},
year={2000},
volume={E83-B},
number={6},
pages={1246-1253},
abstract={A broadband and flexible receiver architecture is investigated for the handheld software defined radio (SDR). The proposed SDR architecture is based on the direct conversion and low intermediate frequency (low-IF) principle with digital channel filtering, which provides the receiver with flexibility for the multi-standard application. This architecture also enables analog-to-digital converter activating essentially in baseband or low frequency so that the clock jitter, which serves as an important subject in the well-known IF sampling method, can be reduced. Basic performance of the proposed architecture has been confirmed by the experimental model.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - Broadband and Flexible Receiver Architecture for Software Defined Radio Terminal Using Direct Conversion and Low-IF Principle
T2 - IEICE TRANSACTIONS on Communications
SP - 1246
EP - 1253
AU - Hiroshi TSURUMI
AU - Hiroshi YOSHIDA
AU - Shoji OTAKA
AU - Hiroshi TANIMOTO
AU - Yasuo SUZUKI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E83-B
IS - 6
JA - IEICE TRANSACTIONS on Communications
Y1 - June 2000
AB - A broadband and flexible receiver architecture is investigated for the handheld software defined radio (SDR). The proposed SDR architecture is based on the direct conversion and low intermediate frequency (low-IF) principle with digital channel filtering, which provides the receiver with flexibility for the multi-standard application. This architecture also enables analog-to-digital converter activating essentially in baseband or low frequency so that the clock jitter, which serves as an important subject in the well-known IF sampling method, can be reduced. Basic performance of the proposed architecture has been confirmed by the experimental model.
ER -
English
