In software defined radio systems, a channelizer plays an important role in extracting the desired signals from a wideband signal. Compared to the conventional methods, the proposed scheme provides a solution to design a digital channelizer extracting the multiple subband signals at different center frequencies with low complexity. To do this, this paper formulates the problem as an optimization problem, which minimizes the required multiplications number subject to the constraints of the ripple in the passbands and the stopbands for single channel and combined multiple channels. In addition, a solution to solve the optimization problem is also presented and the corresponding structure is demonstrated. Simulation results show that the proposed scheme requires smaller number of the multiplications than other conventional methods. Moreover, unlike other methods, this structure can process signals with different bandwidths at different center frequencies simultaneously only by changing the status of the corresponding multiplexers without hardware reimplementation.

Wireless technology improvements have been continually increasing, resulting in greater needs for system design and implementation to accommodate all newly emerging standards. As a result, developing a system that ensures compatibility with numerous wireless systems has sparked interest. As a result of their flexibility and scalability over alternative wireless design options, software-defined radios (SDRs) are highly motivated for wireless device modelling. This research paper delves into the difficulties of designing a reconfigurable multi modulation baseband modulator for SDR systems that can handle a variety of wireless protocols. This research paper has proposed an area-efficient Reconfigurable Baseband Modulator (RBM) model to accomplish multi modulation scheme and resolve the adaptability and flexibility issues with the wide range of wireless standards. This also presents the feasibility of using a multi modulation baseband modulator to maximize adaptability with the least possible computational complexity overhead in the SDR system for next-generation wireless communication systems and provides parameterization. Finally, the re-configurability is evaluated concerning the appropriate symbols generations and analyzed its performance metrics through hardware synthesize results.

With the recent commercialization of fifth-generation mobile communication systems (5G), wireless communications are being used in various fields. Accordingly, the number of situations in which sensitive information, such as personal data is handled in wireless communications is increasing, and so is the demand for confidentiality. To meet this demand, we proposed a chaos-based radio-encryption modulation that combines physical layer confidentiality and channel coding effects, and we have demonstrated its effectiveness through computer simulations. However, there are no demonstrations of performances using real signals. In this study, we constructed a transmission system using Universal Software Radio Peripheral, a type of software-defined radio, and its control software LabVIEW. We conducted wired transmission experiments for the practical use of radio-frequency encrypted modulation. The results showed that a gain of 0.45dB at a bit error rate of 10-3 was obtained for binary phase-shift keying, which has the same transmission efficiency as the proposed method under an additive white Gaussian noise channel. Similarly, a gain of 10dB was obtained under fading conditions. We also evaluated the security ability and demonstrated that chaos modulation has both information-theoretic security and computational security.

Backscatter wireless communications offer advantages such as batteryless operations, small form factor, and radio regulatory exemption sensors. The major challenge ahead of backscatter wireless communications is synchronized multicarrier data collection, which can be realized by rejecting mutual harmonics among backscatters. This paper analyzes the mutual interferences of digitally modulated multicarrier backscatter to find interferences from higher frequency subcarriers to lower frequency subcarriers, which do not take place in analog modulated multicarrier backscatters, is harmful for densely populated subcarriers. This reverse interference distorts the harmonics replica, deteriorating the performance of the existing method, which rejects mutual interference among subcarriers by 5dB processing gain. To solve this problem, this paper analyzes the relationship between subcarrier spacing and reverse interference, and reveals that an alternate channel spacing, with channel separation twice the bandwidth of a subcarrier, can provide reasonably dense subcarrier allocation and can alleviate reverse interference. The idea is examined with prototype sensors in a wired experiment and in an indoor propagation experiment. The results reveal that with alternate channel spacing, the reverse interference practically becomes negligible, and the existing interference rejection method achieves the original processing gain of 5dB with one hundredth packet error rate reduction.

A design method of the differential N-path filter with sampling computation is proposed. It enables the scale of the whole filter to be reduced by approximately half for easier realization. On top of that, the proposed method offers the ability to eliminate the harmonic passbands of the clock frequency and an increase of harmonic rejection. By using the proposed method, previous work involving an 8-path filter can be reduced to 5-path. The proposed differential 5-path filter reduces the scale of the circuit and at the same time has the performance of a 10-path filter from previous work. An example of differential 7-path filter using the same proposed design method is also stated in comparison of the differential 5-path filter. The differential 7-path filter offers the ability to eliminate all the passbands below 10 times the clock frequency with a tradeoff of an increase in circuit scale.

The correct detection of the start of burst is very important in wideband networking radio operation as it directly affects the Time Division Multiple Access (TDMA) adaptive time slot algorithm. In this paper, we propose a robust Data Aided (DA) algorithm for burst detection in a hybrid CDMA/Adaptive TDMA based wideband networking waveform of a software defined radio. The proposed algorithm is based on a novel differentially modulated training sequence designed by using precoding sequence. The training sequence structure and precoding sequence are exploited in the calculation of proposed timing metric which is normalized by the signal energy. The precoding sequence is adequately designed for the timing metric to have a sharp peak. The algorithm shows excellent performance for multiuser scenario. It is shown through computer simulations that by increasing the active users from 1 to 8, the performance degradation is only about 1∼2dB. The proposed algorithm is compared with other algorithms and found to outperform them even in the presence of multipath fading effects. The proposed algorithm has been implemented on Field Programmable Gate Array (FPGA) platform for high data rate applications and it is shown that the results from hardware are identical to the simulation results.

In this paper, we propose a novel Carrier Frequency Offset (CFO) estimation and compensation algorithm applicable to Software Defined Radio (SDR). A two stage estimation algorithm has been proposed as a concatenation of two algorithms namely Modified Maximum Likelihood Data Aided (MMLDA) coarse frequency estimation and sample by sample residual CFO estimation. The second stage tracks the residual offset on sample by sample basis for the whole burst without using preamble. Simulation results are given for Stanford University Interim (SUI) channels to demonstrate the effectiveness of the proposed algorithm in multipath fading channel. The proposed algorithm shows better performance than the conventional two stage algorithms, even for large frequency offsets. The proposed algorithm has been implemented in software on TMS320C64x+ Digital Signal Processor (DSP) core and verified by comparing with simulation results.

Software Defined Radio (SDR) techniques are expected to be among the key technologies of heterogeneous cognitive radio networks for realizing efficient and convenient wireless communications by providing multiple radio services to users and decreasing development costs. In this paper, in order to evaluate the feasibility of SDR modems, we study the amount of computing throughput of a recent wireless system and determine a suitable modem architecture. Firstly, the functions for which SDR techniques provide significant benefits are clarified. Secondly, the computing throughputs are measured under the assumption that a dynamically reconfigurable processor, FlexSwordTM, is employed. Finally, based on a consideration of timing charts, we propose the architecture of an SDR-based modem with FlexSword. The possibility of implementing several wireless systems is also considered.

We present an attractive approach for OFDM transmission using an adaptive pre-FFT equalizer, which can select ICI reduction mode according to channel condition, and a degenerated-inverse-matrix-based channel estimator (DIME), which uses a cyclic sinc-function matrix uniquely determined by transmitted subcarriers. In addition to simulation results, the proposed system with an adaptive pre-FFT equalizer and DIME has been laboratory tested by using a software defined radio (SDR)-based test bed. The simulation and experimental results demonstrated that the system at a rate of more than 100 Mbps can provide a bit error rate of less than 10-3 for a fast multi-path fading channel that has a moving velocity of more than 200 km/h with a delay spread of 1.9 µs (a maximum delay path of 7.3 µs) in the 5-GHz band.

This paper presents a framework of multimode fully digital receiver implementation using direct RF-to-digital conversion. In this architecture the entire band including multiple RF systems is directly converted to digital by a wideband high speed ADC, and the RF systems can be easily switched by only digital signal processing with the minimum analog RF components. The digital RF front-end consists of parallel processing blocks for parallel data streams considering practical ADC's configuration. The RF signals are converted into baseband through digital IF stage and the data rates are made down by two steps of decimation. In this paper, a principle investigation into a dualmode system implementation is presented for simplicity. The circuit resource and the robustness to the spurs (spurious outputs) of an NCO (numerically controlled oscillator) in the proposed design will be presented. The proposed architecture was implemented with an FPGA on the developed prototype system and the operations were also verified.

Software defined radio (SDR) technology has been widely applied for its powerful universality and flexibility in the past decade. To address the issue of bandpass sampling of multiband signals, a novel and efficient method of finding the minimum valid sampling frequency is proposed. Since there are frequency deviations due to the channel effect and hardware instability in actual systems, we also consider the guard-bands between downconverted signal spectra in determining the minimum sampling frequency. In addition, the case that the spectra within the sampled bandwidth are located in inverse placement can be avoided by our proposed method, which will reduce the complexity of the succeeding digital signal process significantly. Simulation results illustrate that the proper minimum sampling frequency can be determined rapidly and accurately.

Through fractional sampling, it is possible to separate multipath components and achieve diversity gain. However, power consumption grows as the sampling rate increases. This paper proposes a novel scheme for OFDM systems that selects the sampling rate according to the channel's frequency response. Numerical results through computer simulation show that the proposed sampling rate selection scheme reduces power consumption by reducing oversampling ratio when delay spread is small.

Various wireless systems are being developed to meet users' needs, and the rapid increase in frequency demand that accompanies the increasing popularity of wireless services means that more effective use of frequency resources is urgently needed. However, existing base stations are making no effort to use frequency resources effectively, and cooperation among wireless system base stations is needed to use frequency resources more effectively. Base stations can cooperate more efficiently if they are able to use multiple channels of many wireless systems simultaneously. We propose an autonomous adaptive base station (AABS) that can switch among various wireless systems the way software defined radio (SDR) base stations do. AABS can autonomously select and use the most suitable wireless system on the basis of user traffic and its hardware resources. Moreover, frequency resources are used effectively because AABS prevents unnecessary radio wave transmission when the number of users in the wireless systems decreases. AABS is also suitable for "multi-link communication" because it can use multiple channels of multiple wireless systems simultaneously. We developed AABS prototype and evaluated its performance. Our experimental and computer simulation results show the performance of AABS and its efficiency.

Implementation of RFID reader/writer on software defined radio is studied in this paper. The target RFID is ISO18000-3 mode 2 which has 8 reply channels for simultaneous communication with 8 different RFID tags. In the software defined radio architecture, the 8 reply channels are sampled at a single A/D converter and separated by digital down converters, whereas conventional RFID architecture has redundant 8 parallel analog down converters. A novel multi-stage transmultiplexing digital down converter is proposed for efficient implementation of multi-channel digital down converter. Moreover the proposed architecture is implemented on a FPGA evaluation board, and validity of the system is confirmed on a real hardware. The proposed architecture can be applied to multi-channel receiver for dynamic spectrum system in the cognitive radio.

"Cognitive radio" and "software-defined radio" (SDR) are today an important consideration in major spectrum debates in the United States. The U.S. drafted its first SDR rules in 2001, and since has continued efforts to resolve potential regulatory concerns and facilitate the benefits of the technology. At the same time, Japan has had a very rich experience in the lab with SDR, with significant achievements on many engineering topics. However, the regulatory state of SDR in Japan has not kept pace with the United States. Likewise cognitive radio, while a topic of inquiry, betrays a different focus. The paper explores why the paths for these technologies have diverged in the U.S. and Japan.

Most digital signal processing (DSP) algorithms for multimedia and communication applications require multiplication and addition operations. Especially matrix-matrix or matrix-vector the multiplications frequently used in DSP implementations needs inner product arithmetic which takes the most processing time. Also multiplications for the DSP algorithms for software defined radio (SDR) applications require different input bitwidths. Therefore, the multiplications for inner product need to be sufficiently flexible in terms of bitwidths to utilize hardware resources efficiently. This paper proposes a novel reconfigurable inner product architecture based on a pipelined adder array, which offers increased flexibility in bitwidths of input arrays. The proposed architecture consists of sixteen 44 multipliers and a pipelined adder array and can compute the inner product of input arrays with any combination of multiples of 4 bitwidths such as 44, 48, 412, ... 1616. Experimental results show that the proposed architecture has latency of maximum 9 clock cycles and throughput of 1 clock cycle for inner product of various bitwidths of input arrays. When TSMC 0.18 µm libraries are used, the chip area and critical path of the proposed architecture are 186,411 gates and 2.79 ns, respectively. The proposed architecture can be applied to a reconfigurable arithmetic engine for real-time SDR system designs.

We previously proposed an architecture for software defined radio called the reconfigurable packet routing-oriented signal processing platform (RPPP). This architecture was suited to wireless signal processing applications, which require radio functions to be selected in real time depending on the transmitted signal. A number of radio standards are used in DSRC systems for vehicle communication and vehicle equipment is required to transmit and receive the radio signals used on each particular occasion. An implementation of RPPP is described in this paper that enables the dynamic handling of two ARIB standards for DSRC. After an explanation of the basic architecture and an analysis of RPPP, the implementation of a reconfigurable DSRC transceiver for ASK and π/4 shift-QPSK is described. The implementation is then discussed, evaluated in terms of the number of logic units needed. We concluded that our platform is 27.6% more efficient in utilizing logic than that achieved with fixed design.

This letter presents an efficient multichannel low-IF reception scheme that improves digital communication quality in the sense of BER performance. Created by simply adding cosine rolloff filters to the conventional multichannel receiver, the proposed receiver achieves much higher accuracy than the conventional one.

A multiple-input multiple-output software defined radio (MIMO-SDR) platform was developed for implementation of MIMO transmission and propagation measurement systems. This platform consists of multiple functional boards for baseband (BB) digital signal processing and frequency conversion of 5 GHz-band radio frequency (RF) signals. The BB boards have capability of arbitrary system implementation by rewriting software on reconfigurable devices such as field programmable gate arrays (FPGAs) and digital signal processors (DSPs). The MIMO-SDR platform employs hybrid implementation architecture by taking advantages of FPGA, DSP, and CPU, where functional blocks with the needs for real-time processing are implemented on the FPGAs/DSPs, and other blocks are processed off-line on the CPU. In order to realize the hybrid implementation, driver software was developed as an application program interface (API) of the MIMO-SDR platform. In this paper, hardware architecture of the developed MIMO-SDR platform and its software implementation architecture are explained. As an application example, implementation of a real-time MIMO channel measurement system and initial measurement results are presented.

In this paper we propose a new reconfigurable signal processing platform for SDR, having capability to change its processing parameters dynamically. On our proposed platform, while the wiring and processing scheme remain fixed, processing parameters and connections between processing modules together with the associated dataflow can be changed. We also demonstrate that our proposed signal processing platform has the new ability of easily composing new signal processing models dynamically, simultaneously with other tasks, and attaining high efficiency of logic usage.