We analyze the timing design methodology for testing chips using a multiple-clock domain scheme. We especially focus on the layout design of the design-for-test (DFT) circuits and the clock network. First, we demonstrate the built-in-self-testing (BIST) scheme for multiple-clock domains. Then, we discuss the layout method that achieves a low clock-skew between different clock domains with a small modification of the original user logic layout. Finally, we evaluate the fault coverage of our large ASIC chips designed using our new methodology. The short design period and high fault coverage of our methodology are confirmed using actual industrial designs. We introduce a viable approach for industrial designs because designers don't have to pay much attention to DFT. Our approach also provides designers with an easy method for LSI debugging and diagnostics.

Transition coverage has been proposed as a measure of two-pattern test capabilities of TPG circuits for use in BIST. This paper investigates experimentally the relationships between transition coverages and actual stuck-open fault coverages in order to reveal what kind of circuits are appropriate for two-pattern testing. Fault simulation was performed using conventional (n-stage) LFSR, 2n-stage LFSR, and one-dimensional cellular automata (CAs) as TPG circuits and such sample circuits as balanced NAND tree and some ISCAS '85 benchmark circuits as CUTs. It was found that CAs which are designed so as to apply exhaustive transitions to any 3-dimensional subspaces can detect high rate of stuck-open faults. Influence of hazards of decreasing the fault coverage is also mentioned.

Multimedia communication services are being made available with the advent of broadband optical fiber networks. As many different services will be accommodated in such networks, network survivability has been recognized to be a crucial concern. In this paper, we propose a new restoration algorithm for ATM networks providing multimedia services. Our proposed restoration algorithm adopts the message bundling scheme of the Multi-Destination Flooding (MDF) algorithm which was previously proposed for STM-based networks to handle catastrophic failures such as multiple link and node failures. Virtual Paths (VP) with the same communication speed are bundled and Operation Administration and Maintenance (OAM) cells are used for communication of restoration messages. In addition, the following modifications are made on the original MDF to improve restoration performance. The pre-cancellation scheme is adopted to arbitrate reservation contention to realize high restoration ratio. The dual queue scheme is applied to avoid congestion of restoration messages. Moreover, the connection control scheme for VPI connections is proposed to prevent alternative routes from being misconnected. This paper describes the design concept of our restoration algorithm, processes in each restoration phase, and the performance evaluation by computer simulation.

This paper describes the nonlinear behavior of CMOS ADC input capacitance. Our SPICE simulation, based on the BSIM3v3 model, shows that the input capacitance of a typical CMOS flash-type ADC (with a single-ended NMOS differential pair preamplifier as the input stage) decreases as its input voltage increases; this is the opposite of what we would expect if we considered only MOSFET gate capacitance nonlinearity. We have found that this can be explained by the nonlinearity of the total effective input capacitance of each differential amplifier stage, taking into account not only MOSFET capacitance but also the fact that the contributions of the gate-source and gate-drain capacitances to the input capacitance of the differential pair change according to its input voltages (an ADC input voltage and a reference voltage). We also discuss design methods to reduce the value of the CMOS ADC effective input capacitance.

This paper describes the formula for dynamic power dissipation of a track/hold circuit as a function of the input frequency, the input amplitude, the sampling frequency, the track/hold duty cycle, the power supply voltage and the hold capacitance for a sinusoidal input.

This paper describes fundamental system of borehole radars and its recent progress in Japan. Early development of borehole radars were carried out for detection of cracks in crystallized rock, however, the fields of applications are expanding to other various objects such as soil and sedimental rocks. Conventionally developed radar systems are not necessarily suitable for these applications and they must be modified. New technologies such as radar polarimetry and radar tomography were also introduced.

Backscatter wireless communications offer advantages such as batteryless operations, small form factor, and radio regulatory exemption sensors. The major challenge ahead of backscatter wireless communications is synchronized multicarrier data collection, which can be realized by rejecting mutual harmonics among backscatters. This paper analyzes the mutual interferences of digitally modulated multicarrier backscatter to find interferences from higher frequency subcarriers to lower frequency subcarriers, which do not take place in analog modulated multicarrier backscatters, is harmful for densely populated subcarriers. This reverse interference distorts the harmonics replica, deteriorating the performance of the existing method, which rejects mutual interference among subcarriers by 5dB processing gain. To solve this problem, this paper analyzes the relationship between subcarrier spacing and reverse interference, and reveals that an alternate channel spacing, with channel separation twice the bandwidth of a subcarrier, can provide reasonably dense subcarrier allocation and can alleviate reverse interference. The idea is examined with prototype sensors in a wired experiment and in an indoor propagation experiment. The results reveal that with alternate channel spacing, the reverse interference practically becomes negligible, and the existing interference rejection method achieves the original processing gain of 5dB with one hundredth packet error rate reduction.

IOG is a link layer protocol specifically designed for the high speed and bandwidth efficient transmission of IPv4 and IPv6 datagrams over optical fibers. That is, IOG is a simple point-to-point packetization protocol over a bit stream with a low bit error rate. MTU of IOG is 1535, which is long enough for the Internet with IPv6 multicast packets and Ethernet frames. IOG has a framing structure of fixed length (2048 bytes) for synchronization, CRCC (Cyclic Redundancy Check Code) and scrambling. A frame consists of 4 bytes of a frame header, 2040 bytes of a frame payload and 4 bytes of a frame trailer for CRCC. CRCC is also used for scrambling. A frame header consists of a 21 bit flag sequence ("011111111111111111110") and a 11 bit packet boundary pointer. A packet has an 11 bit length field and a 21 bit label field. The label field contains an Ethertype or a link layer label. Packets are packed continuously in frame payload. A packet is at least 20 and at most 1535 bytes long. If there are no packets to send, 20 byte packets of Ethertype 0 are sent, which is ignored by the receiver. A packet may be included in two adjacent frames. The packet boundary pointer in a frame header of a frame points to the first packet boundary of the frame, which means that once a frame synchronization is established, packet synchronization is also established. IOG is designed to allow high-speed implementations to enable 32 or 64 bit parallel processing. CRC polynomial of X32 + X2 + X + 1 is newly designed for high-speed 32 or 64 bit parallel calculation and frame wise SECDED (Single Error Correction, Double Error Detection). IOG is applicable to long haul transmission of IP datagrams in Internet backbone and to inter-chip or inter-module transmission of IP datagrams in parallel IP routers.

Revocation is one of the major problems for access control systems. Especially, the revocation cost for the data outsourced in the third party environment such as cloud storage systems. The revocation in the cloud-based access control typically deals with the cryptographic operations that introduce costly overheads for key re-generation, file re-encryption, and key re-distribution. Also, the communication for retrieving files for re-encryption and loading them back to the cloud is another non-trivial cost for data owners. In this paper, we propose a Very Lightweight Proxy Re-Encryption (VL-PRE) scheme to efficiently support attribute-based revocation and policy update in the collaborative data sharing in cloud computing environment. To this end, we propose three-phase VL-PRE protocol including re-encryption key generation, re-encryption key update, and re-encryption key renewal for supporting the optimized attribute revocation and policy update. Finally, we conduct the experiments to evaluate the performance of our VL-PRE and show that it exhibits less computation cost with higher scalability in comparison with existing PRE schemes.

In this paper, we propose a method for enhancing performance of a sequential version of the belief-propagation (BP) decoding algorithm, the group shuffled BP decoding algorithm for low-density parity-check (LDPC) codes. An improved BP decoding algorithm, called the shuffled BP decoding algorithm, decodes each symbol node in serial at each iteration. To reduce the decoding delay of the shuffled BP decoding algorithm, the group shuffled BP decoding algorithm divides all symbol nodes into several groups. In contrast to the original group shuffled BP, which automatically generates groups according to symbol positions, in this paper we propose a method for grouping symbol nodes which generates groups according to the structure of a Tanner graph of the codes. The proposed method can accelerate the convergence of the group shuffled BP algorithm and obtain a lower error rate in a small number of iterations. We show by simulation results that the decoding performance of the proposed method is improved compared with those of the shuffled BP decoding algorithm and the group shuffled BP decoding algorithm.

In this paper, we propose a cross-correlation method applied to multistatic ground penetrating radar (GPR) data sets to detect road pavement damage. Pavement cracks and delamination cause variations in electromagnetic wave propagation. The proposed method can detect velocity change using cross-correlation of data traces at different times. An artificially damaged airport taxiway model was measured, and the method captures the positions of damaged parts.

This paper presents a calibration method for RF switch channels of a near-range multistatic linear array radar. The method allows calibration of the channel transfer functions of the RF switches and antenna transfer functions in frequency domain data, without disconnecting the antennas from the radar system. In addition, the calibration of the channels is independent of the directivities of the transmitting and receiving antennas. We applied the calibration method to a 3D imaging step-frequency radar system at 10-20GHz suitable for the nondestructive inspection of the walls of wooden houses. The measurement range of the radar is limited to 0-240mm, shorter than the antenna array length 480mm. This radar system allows acquiring 3D imaging data with a single scan. Using synthetic aperture radar processing, the structural health of braces inside the walls of wooden houses can be evaluated from the obtained 3D volume images. Based on experiment results, we confirmed that the proposed calibration method significantly improves the subsurface 3D imaging quality. Low intensity ghost images behind the brace target were suppressed, deformations of the target in the volume image were rectified and errors the range distance were corrected.

The finite-difference time-domain (FDTD) method has been widely used in recent years to analyze the propagation and scattering of electromagnetic waves. Because the FDTD method has second-order accuracy in space, its numerical dispersion error arises from truncated higher-order terms of the Taylor expansion. This error increases with the propagation distance in cases of large-scale analysis. The numerical dispersion error is expressed by a dispersion relation equation. It is difficult to solve this nonlinear equation which have many parameters. Consequently, a simple formula is necessary to substitute for the dispersion relation error. In this study, we have obtained a simple formula for the numerical dispersion error of 2-D and 3-D FDTD method in free space propagation.

In computer simulation of a large number of moving objects (MOs), how to enlarge Δt (the interval between the simulation time steps) without introducing causality errors is one of the primary keys to enhancing performance. Causality errors can be avoided by using the same Δt among related MOs when they are in the scene of detection (SoD). But in a large-scale MO simulation, MOs interact with one another in a complicated manner requiring a large calculation cost to predict the beginning time of SoD. In this paper we propose an event-aware dynamic time step synchronization method (DTSS) for distributed MO simulation, which increases Δt without introducing causality errors and speeds up the simulation. DTSS can be implemented with little calculation cost because: (1) DTSS does not calculate the beginning time of SoD exactly, but calculates the time for possible entry into SoD with a simple mechanisim, and (2) MO simulation consists of a "movement"-phase and a "detection"-phase in which the distance-calculation between MOs requires a heavy load, and DTSS utilizes the distance values to calculate Δt. In this paper, we also discuss a suitable HLA based time management mechanism to implement DTSS on a distributed computing environment. In the performance evaluation of DTSS, the calculation cost of DTSS is implemented by using the HLA suitable time management mechanism. The results show that DTSS can be executed within the ideal time plus its 1% over-cost when a basic scenario of war-game simulation is employed. Therefore if the ratio of SoD to the total simulation is small, the execution time is expected to decrease to nearly this ratio. We also introduce the criterion for determining when DTSS is superior to the conventional method by using the performance evaluation results. The results presented in this paper are effectively utilized when DTSS is applied to practical applications.

The Paper describes design and experiment of 2nd cyclotron harmonic peniotron at microwave region using a permanent magnet system. The magnet system using a cylindrical magnet magnetized along the cylindrical axis is designed and fabricated. The 2nd cyclotron harmonic peniotron operating at the π mode in a six vane magnetron waveguide resonator and at 5 GHz was constructed by using the magnet system. The peak electronic efficiency higher than 30% was achieved at the π mode in the resonator.

This paper presents a prototype of a 3D imaging step-frequency radar system at 10-20GHz suitable for the nondestructive inspection of the walls of wooden houses. Using this prototype, it is possible to obtain data for 3D imaging with a single simple scan and make 3D volume images of braces — broken or not — in the walls of wooden houses using synthetic aperture radar processing. The system is a multistatic radar composed of a one-dimensional array antenna (32 transmitting and 32 receiving antennas, which are resistively loaded printed bowtie antennas) and is able to acquire frequency domain data for all the transmitting and receiving antenna pairs, i.e., 32×32=1024 pairs, in 33ms per position. On the basis of comparisons between two array antenna prototype designs, we investigated the optimal distance between a transmitting array and a receiving array to reduce the direct coupling effect. We produced a prototype multistatic radar system and used it to measure different types of wooden targets in two experiments. In the first experiment, we measured plywood bars behind a decorated gypsum board, simulating a broken wooden brace inside a house wall. In the second experiment, we measured a wooden brace made of Japanese cypress as a target inside a model of a typical (wooden) Japanese house wall. The results of both experiments demonstrate the imaging capability of the radar prototype for nondestructive inspection of the insides of wooden house walls.

In order to improve an imaging performance of a sparse array radar system we propose an optimization method to find a new antenna array layout. The method searches for a minimum of the cost function based on a 3D point spread function of the array. We found a solution for the simulated problem in a form of the new layout for the antenna array with more sparse middle-point distribution comparing with initial one.

Chip multiprocessors (CMPs) improve performance by simultaneously executing multiple threads using integrated multiple cores. However, since these cores commonly share one cache, inter-thread cache conflicts often limit the performance improvement by multi-threading. This paper focuses on two causes of inter-thread cache conflicts. In shared caches of CMPs, cached data fetched by one thread are frequently evicted by another thread. Such an eviction, called inter-thread kickout (ITKO), is one of the major causes of inter-thread cache conflicts. The other cause is capacity shortage that occurs when one cache is shared by threads demanding large cache capacities. If the total capacity demanded by the threads exceeds the actual cache capacity, the threads compete to use the limited cache capacity, resulting in capacity shortage. To address inter-thread cache conflicts, we must take into account both ITKOs and capacity shortage. Therefore, this paper proposes a capacity-aware thread scheduling method combined with cache partitioning. In the proposed method, inter-thread cache conflicts due to ITKOs and capacity shortage are decreased by cache partitioning and thread scheduling, respectively. The proposed scheduling method estimates the capacity demand of each thread with an estimation method used in the cache partitioning mechanism. Based on the estimation used for cache partitioning, the thread scheduler decides thread combinations sharing one cache so as to avoid capacity shortage. Evaluation results suggest that the proposed method can improve overall performance by up to 8.1%, and the performance of individual threads by up to 12%. The results also show that both cache partitioning and thread scheduling are indispensable to avoid both ITKOs and capacity shortage simultaneously. Accordingly, the proposed method can significantly reduce the inter-thread cache conflicts and hence improve performance.

A huge amount of information is being accumulated on the Internet as the Internet usage spreads and numbers of Web pages increase. However, it is also becoming very difficult to find required information, even when the information exists. The actual value of the Web is thus much lower than its potential value. In order to solve this problem, technologies which allow machines to handle Web content in an efficient, accurate, and flexible way by using machine-readable metadata are being developed. This paper is a survey of knowledge representation on the Web, and the utilization of metadata and ontology for data integration and information sharing, with a focus on the Semantic Web concept.