Very high-speed off-chip data rates have been difficult to achieve in CMOS technologies. This paper describes an all-CMOS set of I/O buffer circuits, which use current-mode and impedance matching techniques, capable of transmitting off-chip at 1-Gb/s data rates. The circuits are also compatible with voltage-mode signal levels for ECL input and CMOS output curcuits.
Manabu ISHIBE
Shoji OTAKA
Junichi TAKEDA
Shigeru TANAKA
Yoshiaki TOYOSHIMA
Satoru TAKATSUKA
Shoichi SHIMIZU
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Manabu ISHIBE, Shoji OTAKA, Junichi TAKEDA, Shigeru TANAKA, Yoshiaki TOYOSHIMA, Satoru TAKATSUKA, Shoichi SHIMIZU, "High-Speed CMOS I/O Buffer Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E75-C, no. 4, pp. 569-571, April 1992, doi: .
Abstract: Very high-speed off-chip data rates have been difficult to achieve in CMOS technologies. This paper describes an all-CMOS set of I/O buffer circuits, which use current-mode and impedance matching techniques, capable of transmitting off-chip at 1-Gb/s data rates. The circuits are also compatible with voltage-mode signal levels for ECL input and CMOS output curcuits.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_4_569/_p
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@ARTICLE{e75-c_4_569,
author={Manabu ISHIBE, Shoji OTAKA, Junichi TAKEDA, Shigeru TANAKA, Yoshiaki TOYOSHIMA, Satoru TAKATSUKA, Shoichi SHIMIZU, },
journal={IEICE TRANSACTIONS on Electronics},
title={High-Speed CMOS I/O Buffer Circuits},
year={1992},
volume={E75-C},
number={4},
pages={569-571},
abstract={Very high-speed off-chip data rates have been difficult to achieve in CMOS technologies. This paper describes an all-CMOS set of I/O buffer circuits, which use current-mode and impedance matching techniques, capable of transmitting off-chip at 1-Gb/s data rates. The circuits are also compatible with voltage-mode signal levels for ECL input and CMOS output curcuits.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - High-Speed CMOS I/O Buffer Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 569
EP - 571
AU - Manabu ISHIBE
AU - Shoji OTAKA
AU - Junichi TAKEDA
AU - Shigeru TANAKA
AU - Yoshiaki TOYOSHIMA
AU - Satoru TAKATSUKA
AU - Shoichi SHIMIZU
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1992
AB - Very high-speed off-chip data rates have been difficult to achieve in CMOS technologies. This paper describes an all-CMOS set of I/O buffer circuits, which use current-mode and impedance matching techniques, capable of transmitting off-chip at 1-Gb/s data rates. The circuits are also compatible with voltage-mode signal levels for ECL input and CMOS output curcuits.
ER -