A novel spur cancelled clock generator (SCCG) capable of recovering RX sensitivity degradations caused by digital clocks in wireless SoCs is presented. Clock spurs that degrade RX sensitivities are canceled by applying the SCCG to digital circuits or ADCs. The SCCG is integrated into a Bluetooth Low Energy (BLE) SoC fabricated in a 65 nm CMOS process. A measured clock spur reduction of 34 dB and an RX sensitivity recovery of 5 dB are achieved by the proposed SCCG. The power consumption and occupied area of the SCCG is only 18 µW and 40 μm × 120 μm, respectively.

Integrated 900-MHz ISM band transceiver LSI for analog cordless telephone has been realized by cost-effective process technology with sufficient performance. This LSI consisted of fully integrated transceiver, from RF-LNA to audio amplifier for RX chain, from microphone's amplifier to RF-PA for TX chain, and integrated RX- and TX-LO consisting of PLLs and VCOs. In view of narrow signal bandwidth with analog modulation, extremely low phase noise at low offset frequency from carrier was required for integrated VCO. Also, in view of fully duplex operations, signal isolation between TX and RX was required. Despite such a high integration and high performance, chip cost had to be minimized for low-cost applications. The 12-dB SINAD RX sensitivity was -111.2 dBm, the output power of TX was +3 dBm, and the phase noise of integrated VCO was -77 dBc/Hz at 3 kHz offset away from carrier. The current consumption at fully duplex operation was 76 mA at 3.6 V power supply. The chip was realized by 0.8 µm standard silicon BiCMOS process.