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32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor
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Summary :
A 32-bit arithmetic logic unit (ALU) is designed for a rapid single flux quantum (RSFQ) bit-parallel processor. In the ALU, clocked gates are partially replaced by clockless gates. This reduces the number of D flip flops (DFFs) required for path balancing. The number of clocked gates, including DFFs, is reduced by approximately 40 %, and size of the clock distribution network is reduced. The number of pipeline stages becomes modest. The layout design of the ALU and simulation results show the effectiveness of using clockless gates in wide datapath circuits.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E105-C No.6 pp.245-250
- Publication Date
- 2022/06/01
- Publicized
- 2021/12/03
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.2021SEP0005
- Type of Manuscript
- Special Section INVITED PAPER (Special Section on Progress & Trend of Superconductor-based Computers)
- Category
Authors
Takahiro KAWAGUCHI
Kyoto University
Naofumi TAKAGI
Kyoto University
Keyword
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Takahiro KAWAGUCHI, Naofumi TAKAGI, "32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor" in IEICE TRANSACTIONS on Electronics,
vol. E105-C, no. 6, pp. 245-250, June 2022, doi: 10.1587/transele.2021SEP0005.
Abstract: A 32-bit arithmetic logic unit (ALU) is designed for a rapid single flux quantum (RSFQ) bit-parallel processor. In the ALU, clocked gates are partially replaced by clockless gates. This reduces the number of D flip flops (DFFs) required for path balancing. The number of clocked gates, including DFFs, is reduced by approximately 40 %, and size of the clock distribution network is reduced. The number of pipeline stages becomes modest. The layout design of the ALU and simulation results show the effectiveness of using clockless gates in wide datapath circuits.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2021SEP0005/_p
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@ARTICLE{e105-c_6_245,
author={Takahiro KAWAGUCHI, Naofumi TAKAGI, },
journal={IEICE TRANSACTIONS on Electronics},
title={32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor},
year={2022},
volume={E105-C},
number={6},
pages={245-250},
abstract={A 32-bit arithmetic logic unit (ALU) is designed for a rapid single flux quantum (RSFQ) bit-parallel processor. In the ALU, clocked gates are partially replaced by clockless gates. This reduces the number of D flip flops (DFFs) required for path balancing. The number of clocked gates, including DFFs, is reduced by approximately 40 %, and size of the clock distribution network is reduced. The number of pipeline stages becomes modest. The layout design of the ALU and simulation results show the effectiveness of using clockless gates in wide datapath circuits.},
keywords={},
doi={10.1587/transele.2021SEP0005},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - 32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor
T2 - IEICE TRANSACTIONS on Electronics
SP - 245
EP - 250
AU - Takahiro KAWAGUCHI
AU - Naofumi TAKAGI
PY - 2022
DO - 10.1587/transele.2021SEP0005
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E105-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2022
AB - A 32-bit arithmetic logic unit (ALU) is designed for a rapid single flux quantum (RSFQ) bit-parallel processor. In the ALU, clocked gates are partially replaced by clockless gates. This reduces the number of D flip flops (DFFs) required for path balancing. The number of clocked gates, including DFFs, is reduced by approximately 40 %, and size of the clock distribution network is reduced. The number of pipeline stages becomes modest. The layout design of the ALU and simulation results show the effectiveness of using clockless gates in wide datapath circuits.
ER -
English
