IEICE TRANSACTIONS on Electronics
A 24 mW 5.7 Gbps Dual Frequency Conversion Demodulator for Impulse Radio with the First Sidelobe
Summary :
This paper presents a modulation scheme for impulse radio that uses the first sidelobe for transmitting a non-return-to-zero baseband signal and the implementation of a dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that realized by binary phase-shift keying modulation and does not require an up-converter in the transmitter. The dual frequency conversion demodulator compensates for the spectrum distortion caused by the frequency response of the circuits and channel. The effect of frequency compensation is analytically studied. The fabricated demodulator test chip of 65 nm CMOS achieves clock and data recovery at 5.7 Gbps with a power consumption of 24 mW.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E99-C No.10 pp.1164-1173
- Publication Date
- 2016/10/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E99.C.1164
- Type of Manuscript
- Special Section PAPER (Special Section on Microwave and Millimeter-Wave Technology)
- Category
Authors
Kaoru KOHIRA
Keio University
Naoki KITAZAWA
Keio University
Hiroki ISHIKURO
Keio University
Keyword
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Kaoru KOHIRA, Naoki KITAZAWA, Hiroki ISHIKURO, "A 24 mW 5.7 Gbps Dual Frequency Conversion Demodulator for Impulse Radio with the First Sidelobe" in IEICE TRANSACTIONS on Electronics,
vol. E99-C, no. 10, pp. 1164-1173, October 2016, doi: 10.1587/transele.E99.C.1164.
Abstract: This paper presents a modulation scheme for impulse radio that uses the first sidelobe for transmitting a non-return-to-zero baseband signal and the implementation of a dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that realized by binary phase-shift keying modulation and does not require an up-converter in the transmitter. The dual frequency conversion demodulator compensates for the spectrum distortion caused by the frequency response of the circuits and channel. The effect of frequency compensation is analytically studied. The fabricated demodulator test chip of 65 nm CMOS achieves clock and data recovery at 5.7 Gbps with a power consumption of 24 mW.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.1164/_p
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@ARTICLE{e99-c_10_1164,
author={Kaoru KOHIRA, Naoki KITAZAWA, Hiroki ISHIKURO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 24 mW 5.7 Gbps Dual Frequency Conversion Demodulator for Impulse Radio with the First Sidelobe},
year={2016},
volume={E99-C},
number={10},
pages={1164-1173},
abstract={This paper presents a modulation scheme for impulse radio that uses the first sidelobe for transmitting a non-return-to-zero baseband signal and the implementation of a dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that realized by binary phase-shift keying modulation and does not require an up-converter in the transmitter. The dual frequency conversion demodulator compensates for the spectrum distortion caused by the frequency response of the circuits and channel. The effect of frequency compensation is analytically studied. The fabricated demodulator test chip of 65 nm CMOS achieves clock and data recovery at 5.7 Gbps with a power consumption of 24 mW.},
keywords={},
doi={10.1587/transele.E99.C.1164},
ISSN={1745-1353},
month={October},}
Copy
TY - JOUR
TI - A 24 mW 5.7 Gbps Dual Frequency Conversion Demodulator for Impulse Radio with the First Sidelobe
T2 - IEICE TRANSACTIONS on Electronics
SP - 1164
EP - 1173
AU - Kaoru KOHIRA
AU - Naoki KITAZAWA
AU - Hiroki ISHIKURO
PY - 2016
DO - 10.1587/transele.E99.C.1164
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2016
AB - This paper presents a modulation scheme for impulse radio that uses the first sidelobe for transmitting a non-return-to-zero baseband signal and the implementation of a dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that realized by binary phase-shift keying modulation and does not require an up-converter in the transmitter. The dual frequency conversion demodulator compensates for the spectrum distortion caused by the frequency response of the circuits and channel. The effect of frequency compensation is analytically studied. The fabricated demodulator test chip of 65 nm CMOS achieves clock and data recovery at 5.7 Gbps with a power consumption of 24 mW.
ER -
English
