4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop

Tetsuya IIZUKA; Meikan CHIN; Toru NAKURA; Kunihiro ASADA

doi:10.1587/transele.2021CTP0001

IEICE TRANSACTIONS on Electronics

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4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop

Tetsuya IIZUKA, Meikan CHIN, Toru NAKURA, Kunihiro ASADA

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This paper proposes a reference-clock-less quick-start-up CDR that resumes from a stand-by state only with a 4-bit preamble utilizing a phase generator with an embedded Time-to-Digital Converter (TDC). The phase generator detects 1-UI time interval by using its internal TDC and works as a self-tunable digitally-controlled delay line. Once the phase generator coarsely tunes the recovered clock period, then the residual time difference is finely tuned by a fine Digital-to-Time Converter (DTC). Since the tuning resolution of the fine DTC is matched by design with the time resolution of the TDC that is used as a phase detector, the fine tuning completes instantaneously. After the initial coarse and fine delay tuning, the feedback loop for frequency tracking is activated in order to improve Consecutive Identical Digits (CID) tolerance of the CDR. By applying the frequency tracking architecture, the proposed CDR achieves more than 100bits of CID tolerance. A prototype implemented in a 65nm bulk CMOS process operates at a 0.9-2.15Gbps continuous rate. It consumes 5.1-8.4mA in its active state and 42μA leakage current in its stand-by state from a 1.0V supply.

Publication: IEICE TRANSACTIONS on Electronics Vol.E105-C No.10 pp.544-551

Publication Date: 2022/10/01

Publicized: 2022/04/11

Online ISSN: 1745-1353

DOI: 10.1587/transele.2021CTP0001

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)

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Authors

Tetsuya IIZUKA
  The University of Tokyo,the University of Tokyo
Meikan CHIN
  the University of Tokyo
Toru NAKURA
  Fukuoka University
Kunihiro ASADA
  the University of Tokyo

Keyword

clock-and-data recovery (CDR), time-to-digital converter (TDC), serial communication, quick start-up, internet-of-things

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Tetsuya IIZUKA, Meikan CHIN, Toru NAKURA, Kunihiro ASADA, "4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop" in IEICE TRANSACTIONS on Electronics, vol. E105-C, no. 10, pp. 544-551, October 2022, doi: 10.1587/transele.2021CTP0001.
Abstract: This paper proposes a reference-clock-less quick-start-up CDR that resumes from a stand-by state only with a 4-bit preamble utilizing a phase generator with an embedded Time-to-Digital Converter (TDC). The phase generator detects 1-UI time interval by using its internal TDC and works as a self-tunable digitally-controlled delay line. Once the phase generator coarsely tunes the recovered clock period, then the residual time difference is finely tuned by a fine Digital-to-Time Converter (DTC). Since the tuning resolution of the fine DTC is matched by design with the time resolution of the TDC that is used as a phase detector, the fine tuning completes instantaneously. After the initial coarse and fine delay tuning, the feedback loop for frequency tracking is activated in order to improve Consecutive Identical Digits (CID) tolerance of the CDR. By applying the frequency tracking architecture, the proposed CDR achieves more than 100bits of CID tolerance. A prototype implemented in a 65nm bulk CMOS process operates at a 0.9-2.15Gbps continuous rate. It consumes 5.1-8.4mA in its active state and 42μA leakage current in its stand-by state from a 1.0V supply.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2021CTP0001/_p

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@ARTICLE{e105-c_10_544,
author={Tetsuya IIZUKA, Meikan CHIN, Toru NAKURA, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop},
year={2022},
volume={E105-C},
number={10},
pages={544-551},
abstract={This paper proposes a reference-clock-less quick-start-up CDR that resumes from a stand-by state only with a 4-bit preamble utilizing a phase generator with an embedded Time-to-Digital Converter (TDC). The phase generator detects 1-UI time interval by using its internal TDC and works as a self-tunable digitally-controlled delay line. Once the phase generator coarsely tunes the recovered clock period, then the residual time difference is finely tuned by a fine Digital-to-Time Converter (DTC). Since the tuning resolution of the fine DTC is matched by design with the time resolution of the TDC that is used as a phase detector, the fine tuning completes instantaneously. After the initial coarse and fine delay tuning, the feedback loop for frequency tracking is activated in order to improve Consecutive Identical Digits (CID) tolerance of the CDR. By applying the frequency tracking architecture, the proposed CDR achieves more than 100bits of CID tolerance. A prototype implemented in a 65nm bulk CMOS process operates at a 0.9-2.15Gbps continuous rate. It consumes 5.1-8.4mA in its active state and 42μA leakage current in its stand-by state from a 1.0V supply.},
keywords={},
doi={10.1587/transele.2021CTP0001},
ISSN={1745-1353},
month={October},}

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TY - JOUR
TI - 4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop
T2 - IEICE TRANSACTIONS on Electronics
SP - 544
EP - 551
AU - Tetsuya IIZUKA
AU - Meikan CHIN
AU - Toru NAKURA
AU - Kunihiro ASADA
PY - 2022
DO - 10.1587/transele.2021CTP0001
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E105-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2022
AB - This paper proposes a reference-clock-less quick-start-up CDR that resumes from a stand-by state only with a 4-bit preamble utilizing a phase generator with an embedded Time-to-Digital Converter (TDC). The phase generator detects 1-UI time interval by using its internal TDC and works as a self-tunable digitally-controlled delay line. Once the phase generator coarsely tunes the recovered clock period, then the residual time difference is finely tuned by a fine Digital-to-Time Converter (DTC). Since the tuning resolution of the fine DTC is matched by design with the time resolution of the TDC that is used as a phase detector, the fine tuning completes instantaneously. After the initial coarse and fine delay tuning, the feedback loop for frequency tracking is activated in order to improve Consecutive Identical Digits (CID) tolerance of the CDR. By applying the frequency tracking architecture, the proposed CDR achieves more than 100bits of CID tolerance. A prototype implemented in a 65nm bulk CMOS process operates at a 0.9-2.15Gbps continuous rate. It consumes 5.1-8.4mA in its active state and 42μA leakage current in its stand-by state from a 1.0V supply.
ER -

IEICE TRANSACTIONS on Electronics