IEICE TRANSACTIONS on Information
A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line
Summary :
In this paper, we propose a method to diagnose a bridging fault between a clock line and a gate signal line. Assuming that scan based flush tests are applied, we perform fault simulation to deduce candidate faults. By analyzing fault behavior, it is revealed that faulty clock waveforms depend on the timing of the signal transition on a gate signal line which is bridged. In the fault simulation, a backward sensitized path tracing approach is introduced to calculate the timing of signal transitions. Experimental results show that the proposed method deduces candidate faults more accurately than our previous method.
- Publication
- IEICE TRANSACTIONS on Information Vol.E100-D No.9 pp.2224-2227
- Publication Date
- 2017/09/01
- Publicized
- 2017/06/12
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2016EDL8210
- Type of Manuscript
- LETTER
- Category
- Dependable Computing
Authors
Yoshinobu HIGAMI
Ehime University
Senling WANG
Ehime University
Hiroshi TAKAHASHI
Ehime University
Shin-ya KOBAYASHI
Ehime University
Kewal K. SALUJA
University of Wisconsin - Madison
Keyword
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Yoshinobu HIGAMI, Senling WANG, Hiroshi TAKAHASHI, Shin-ya KOBAYASHI, Kewal K. SALUJA, "A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line" in IEICE TRANSACTIONS on Information,
vol. E100-D, no. 9, pp. 2224-2227, September 2017, doi: 10.1587/transinf.2016EDL8210.
Abstract: In this paper, we propose a method to diagnose a bridging fault between a clock line and a gate signal line. Assuming that scan based flush tests are applied, we perform fault simulation to deduce candidate faults. By analyzing fault behavior, it is revealed that faulty clock waveforms depend on the timing of the signal transition on a gate signal line which is bridged. In the fault simulation, a backward sensitized path tracing approach is introduced to calculate the timing of signal transitions. Experimental results show that the proposed method deduces candidate faults more accurately than our previous method.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2016EDL8210/_p
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@ARTICLE{e100-d_9_2224,
author={Yoshinobu HIGAMI, Senling WANG, Hiroshi TAKAHASHI, Shin-ya KOBAYASHI, Kewal K. SALUJA, },
journal={IEICE TRANSACTIONS on Information},
title={A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line},
year={2017},
volume={E100-D},
number={9},
pages={2224-2227},
abstract={In this paper, we propose a method to diagnose a bridging fault between a clock line and a gate signal line. Assuming that scan based flush tests are applied, we perform fault simulation to deduce candidate faults. By analyzing fault behavior, it is revealed that faulty clock waveforms depend on the timing of the signal transition on a gate signal line which is bridged. In the fault simulation, a backward sensitized path tracing approach is introduced to calculate the timing of signal transitions. Experimental results show that the proposed method deduces candidate faults more accurately than our previous method.},
keywords={},
doi={10.1587/transinf.2016EDL8210},
ISSN={1745-1361},
month={September},}
Copy
TY - JOUR
TI - A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line
T2 - IEICE TRANSACTIONS on Information
SP - 2224
EP - 2227
AU - Yoshinobu HIGAMI
AU - Senling WANG
AU - Hiroshi TAKAHASHI
AU - Shin-ya KOBAYASHI
AU - Kewal K. SALUJA
PY - 2017
DO - 10.1587/transinf.2016EDL8210
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E100-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2017
AB - In this paper, we propose a method to diagnose a bridging fault between a clock line and a gate signal line. Assuming that scan based flush tests are applied, we perform fault simulation to deduce candidate faults. By analyzing fault behavior, it is revealed that faulty clock waveforms depend on the timing of the signal transition on a gate signal line which is bridged. In the fault simulation, a backward sensitized path tracing approach is introduced to calculate the timing of signal transitions. Experimental results show that the proposed method deduces candidate faults more accurately than our previous method.
ER -
English
