We studied minority carrier collection in high-density stacked-capacitor DRAM cells using a three-dimensional device simulator. We estimated the collected charge for incident angle, location, and junction size and showed that, compared to the conventional structure by a twin-well process, an n-well-guarded cell array fabricated using a triple-well process effectively reduced the charge injected into cells. The reduction was because the n-well absorbed most of the electrons. A so-called "size-effect" did exist and smaller junctions performed better. We concluded that storage capacitance in a 256 M-bit DRAM cell could be reduced, compared to that in previous devices, which would, in turn, help reduce costs in fabricating high-density DRAM.

High performance I/O circuits for fast memory devices such as Synchronous DRAMs were studied. For a TTL interface, the effect of capacitive loading must increase as I/O speed is increased, and signal termination is required for frequencies over 100 MHz. For this reason, industry-proposed alternative interface approaches such as GTL and CTT were investigated using experimental test devices. The results showed that open-drain type drivers have a problem; as the frequency increases, the high-level output voltage becomes degraded. In contrast, a push-pull driver T-LVTTL (Terminated Low Voltage TTL), developed as an implementation of the CTT interface specification, was found to be suitable for high-speed data transfer. A high-speed bus driver circuit connecting an impedance element in series to the stub is proposed as an application of T-LVTTL. Simulated results showed that this scheme greatly improves the signal integrity of memory bus systems; the operating frequency could very well be the highest among several schemes discussed as candidates for the post-LVTTL standard interface.

We report two new timing control methods for high-speed synchronous interfaces in view of their application to high-speed synchronous DRAMs. These two new circuits are the measure-controlled DLL and the register-controlled DLL.We quantitatively analyzed the minimum operational cycle time for a synchronous interface, and related the minimum bus cycle time to two factors; the bus-to-clock timing skew, and the unit delay time of the DLL. Based on this analysis, we concluded that the I/O performance can be beyond 400 MHz by suppressing both factors to less than 200 ps.