IEICE TRANSACTIONS on Electronics
Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface
Summary :
We report two new timing control methods for high-speed synchronous interfaces in view of their application to high-speed synchronous DRAMs. These two new circuits are the measure-controlled DLL and the register-controlled DLL.We quantitatively analyzed the minimum operational cycle time for a synchronous interface, and related the minimum bus cycle time to two factors; the bus-to-clock timing skew, and the unit delay time of the DLL. Based on this analysis, we concluded that the I/O performance can be beyond 400 MHz by suppressing both factors to less than 200 ps.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E79-C No.6 pp.798-807
- Publication Date
- 1996/06/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on ULSI Memory Technology)
- Category
- Dynamic RAMs
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Yoshinori OKAJIMA, Masao TAGUCHI, Miki YANAGAWA, Koichi NISHIMURA, Osamu HAMADA, "Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface" in IEICE TRANSACTIONS on Electronics,
vol. E79-C, no. 6, pp. 798-807, June 1996, doi: .
Abstract: We report two new timing control methods for high-speed synchronous interfaces in view of their application to high-speed synchronous DRAMs. These two new circuits are the measure-controlled DLL and the register-controlled DLL.We quantitatively analyzed the minimum operational cycle time for a synchronous interface, and related the minimum bus cycle time to two factors; the bus-to-clock timing skew, and the unit delay time of the DLL. Based on this analysis, we concluded that the I/O performance can be beyond 400 MHz by suppressing both factors to less than 200 ps.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_6_798/_p
Copy
@ARTICLE{e79-c_6_798,
author={Yoshinori OKAJIMA, Masao TAGUCHI, Miki YANAGAWA, Koichi NISHIMURA, Osamu HAMADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface},
year={1996},
volume={E79-C},
number={6},
pages={798-807},
abstract={We report two new timing control methods for high-speed synchronous interfaces in view of their application to high-speed synchronous DRAMs. These two new circuits are the measure-controlled DLL and the register-controlled DLL.We quantitatively analyzed the minimum operational cycle time for a synchronous interface, and related the minimum bus cycle time to two factors; the bus-to-clock timing skew, and the unit delay time of the DLL. Based on this analysis, we concluded that the I/O performance can be beyond 400 MHz by suppressing both factors to less than 200 ps.},
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface
T2 - IEICE TRANSACTIONS on Electronics
SP - 798
EP - 807
AU - Yoshinori OKAJIMA
AU - Masao TAGUCHI
AU - Miki YANAGAWA
AU - Koichi NISHIMURA
AU - Osamu HAMADA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1996
AB - We report two new timing control methods for high-speed synchronous interfaces in view of their application to high-speed synchronous DRAMs. These two new circuits are the measure-controlled DLL and the register-controlled DLL.We quantitatively analyzed the minimum operational cycle time for a synchronous interface, and related the minimum bus cycle time to two factors; the bus-to-clock timing skew, and the unit delay time of the DLL. Based on this analysis, we concluded that the I/O performance can be beyond 400 MHz by suppressing both factors to less than 200 ps.
ER -
English
