We propose a low-power eFuse one-time programmable (OTP) memory IP based on a bipolar CMOS DMOS (BCD) process. It is an eFuse OTP memory cell which uses separate transistors that are optimized in program and in read mode. The eFuse cell also uses poly-silicon gates having co-silicide. An asynchronous interface and a separate I/O method are used for the low-power and small-area eFuse OTP memory IP. Additionally, we propose a new circuit protecting a short-circuit current in the VDD-to-VIO voltage level translator circuit while the VDD voltage is being generated by the voltage regulator at power-up. A digital sensing circuit using clocked inverters is used to sense a bit-line (BL) datum. Furthermore, the poly-silicon of the IP is split into n+ poly-silicon and p+ poly-silicon to optimize the eFuse link. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18 µm BCD process is 283.565524.180 µm2. It is measured by manufactured test IPs with Dongbu HiTek's 0.18 µm BCD process that the programming voltage of the n+ gate poly-silicon is about 0.1 V less than that of the p+ gate poly-silicon.

We report two new timing control methods for high-speed synchronous interfaces in view of their application to high-speed synchronous DRAMs. These two new circuits are the measure-controlled DLL and the register-controlled DLL.We quantitatively analyzed the minimum operational cycle time for a synchronous interface, and related the minimum bus cycle time to two factors; the bus-to-clock timing skew, and the unit delay time of the DLL. Based on this analysis, we concluded that the I/O performance can be beyond 400 MHz by suppressing both factors to less than 200 ps.