A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die

Yoshiyuki HARAGUCHI; Toshihiko HIROSE; Motomu UKITA; Tomohisa WADA; Masanao EINO; Minoru SAITO; Michihiro YAMADA; Akihiko YASUOKA

A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die

Yoshiyuki HARAGUCHI, Toshihiko HIROSE, Motomu UKITA, Tomohisa WADA, Masanao EINO, Minoru SAITO, Michihiro YAMADA, Akihiko YASUOKA

Full Text Views

0

Cite this

Summary :

This paper describes a new hierarchical bit line organization utilizing a T-shaped bit line(H-BLT) and its practical implementation in a 4-Mb SRAM using a 0.4µm CMOS process. The H-BLT has reduced the number of I/O circuits for multiplexers, sense amplifiers and write drivers, resulting in an efficient multiple blockdivision of the memory cell array. The size of the SRAM die was reduced by 14% without an access penalty. The active current is 30mA at 5 V and 10 MHz. The typical address access time is 35 ns with a 4.5 V supply voltage and a 30 pF load capacitance. The operating voltage range is 2.5 V to 6.0 V. H-BLT is a bright and useful architecture for the high density SRAMs of the future.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.6 pp.743-749

Publication Date: 1996/06/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology)

Category: Static RAMs

Cite this

Copy

Yoshiyuki HARAGUCHI, Toshihiko HIROSE, Motomu UKITA, Tomohisa WADA, Masanao EINO, Minoru SAITO, Michihiro YAMADA, Akihiko YASUOKA, "A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 6, pp. 743-749, June 1996, doi: .
Abstract: This paper describes a new hierarchical bit line organization utilizing a T-shaped bit line(H-BLT) and its practical implementation in a 4-Mb SRAM using a 0.4µm CMOS process. The H-BLT has reduced the number of I/O circuits for multiplexers, sense amplifiers and write drivers, resulting in an efficient multiple blockdivision of the memory cell array. The size of the SRAM die was reduced by 14% without an access penalty. The active current is 30mA at 5 V and 10 MHz. The typical address access time is 35 ns with a 4.5 V supply voltage and a 30 pF load capacitance. The operating voltage range is 2.5 V to 6.0 V. H-BLT is a bright and useful architecture for the high density SRAMs of the future.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_6_743/_p

Copy

@ARTICLE{e79-c_6_743,
author={Yoshiyuki HARAGUCHI, Toshihiko HIROSE, Motomu UKITA, Tomohisa WADA, Masanao EINO, Minoru SAITO, Michihiro YAMADA, Akihiko YASUOKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die},
year={1996},
volume={E79-C},
number={6},
pages={743-749},
abstract={This paper describes a new hierarchical bit line organization utilizing a T-shaped bit line(H-BLT) and its practical implementation in a 4-Mb SRAM using a 0.4µm CMOS process. The H-BLT has reduced the number of I/O circuits for multiplexers, sense amplifiers and write drivers, resulting in an efficient multiple blockdivision of the memory cell array. The size of the SRAM die was reduced by 14% without an access penalty. The active current is 30mA at 5 V and 10 MHz. The typical address access time is 35 ns with a 4.5 V supply voltage and a 30 pF load capacitance. The operating voltage range is 2.5 V to 6.0 V. H-BLT is a bright and useful architecture for the high density SRAMs of the future.},
keywords={},
doi={},
ISSN={},
month={June},}

Copy

TY - JOUR
TI - A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die
T2 - IEICE TRANSACTIONS on Electronics
SP - 743
EP - 749
AU - Yoshiyuki HARAGUCHI
AU - Toshihiko HIROSE
AU - Motomu UKITA
AU - Tomohisa WADA
AU - Masanao EINO
AU - Minoru SAITO
AU - Michihiro YAMADA
AU - Akihiko YASUOKA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1996
AB - This paper describes a new hierarchical bit line organization utilizing a T-shaped bit line(H-BLT) and its practical implementation in a 4-Mb SRAM using a 0.4µm CMOS process. The H-BLT has reduced the number of I/O circuits for multiplexers, sense amplifiers and write drivers, resulting in an efficient multiple blockdivision of the memory cell array. The size of the SRAM die was reduced by 14% without an access penalty. The active current is 30mA at 5 V and 10 MHz. The typical address access time is 35 ns with a 4.5 V supply voltage and a 30 pF load capacitance. The operating voltage range is 2.5 V to 6.0 V. H-BLT is a bright and useful architecture for the high density SRAMs of the future.
ER -