IEICE TRANSACTIONS on Electronics
A Novel Sensing Scheme with On-Chip Page Copy for Flexible Voltage NAND Flash Memories
Summary :
This paper describes a newly developed sensing scheme with a bit-by-bit program verify technique for NAND flash disk systems. This sensing scheme achieves good noise immunity for large capacitive coupling between bitlines, and makes NAND flash memories operable for flexible power supply voltages including both 3.3V and 5V. A highly reliable read operation is performed for power supply voltages above 3V and a bitline-bitline coupling ratio below 50%. The sensing scheme also achieves an intelligent page copy function with 20% reduction in time and without external buffers and CPU resources.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E79-C No.6 pp.836-844
- Publication Date
- 1996/06/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on ULSI Memory Technology)
- Category
- Nonvolatile memories
Authors
Keyword
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Hiroshi NAKAMURA, Jun-ichi MIYAMOTO, Ken-ichi IMAMIYA, Yoshihisa IWATA, Yoshihisa SUGIURA, Hideko OODAIRA, "A Novel Sensing Scheme with On-Chip Page Copy for Flexible Voltage NAND Flash Memories" in IEICE TRANSACTIONS on Electronics,
vol. E79-C, no. 6, pp. 836-844, June 1996, doi: .
Abstract: This paper describes a newly developed sensing scheme with a bit-by-bit program verify technique for NAND flash disk systems. This sensing scheme achieves good noise immunity for large capacitive coupling between bitlines, and makes NAND flash memories operable for flexible power supply voltages including both 3.3V and 5V. A highly reliable read operation is performed for power supply voltages above 3V and a bitline-bitline coupling ratio below 50%. The sensing scheme also achieves an intelligent page copy function with 20% reduction in time and without external buffers and CPU resources.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_6_836/_p
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@ARTICLE{e79-c_6_836,
author={Hiroshi NAKAMURA, Jun-ichi MIYAMOTO, Ken-ichi IMAMIYA, Yoshihisa IWATA, Yoshihisa SUGIURA, Hideko OODAIRA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Novel Sensing Scheme with On-Chip Page Copy for Flexible Voltage NAND Flash Memories},
year={1996},
volume={E79-C},
number={6},
pages={836-844},
abstract={This paper describes a newly developed sensing scheme with a bit-by-bit program verify technique for NAND flash disk systems. This sensing scheme achieves good noise immunity for large capacitive coupling between bitlines, and makes NAND flash memories operable for flexible power supply voltages including both 3.3V and 5V. A highly reliable read operation is performed for power supply voltages above 3V and a bitline-bitline coupling ratio below 50%. The sensing scheme also achieves an intelligent page copy function with 20% reduction in time and without external buffers and CPU resources.},
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - A Novel Sensing Scheme with On-Chip Page Copy for Flexible Voltage NAND Flash Memories
T2 - IEICE TRANSACTIONS on Electronics
SP - 836
EP - 844
AU - Hiroshi NAKAMURA
AU - Jun-ichi MIYAMOTO
AU - Ken-ichi IMAMIYA
AU - Yoshihisa IWATA
AU - Yoshihisa SUGIURA
AU - Hideko OODAIRA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1996
AB - This paper describes a newly developed sensing scheme with a bit-by-bit program verify technique for NAND flash disk systems. This sensing scheme achieves good noise immunity for large capacitive coupling between bitlines, and makes NAND flash memories operable for flexible power supply voltages including both 3.3V and 5V. A highly reliable read operation is performed for power supply voltages above 3V and a bitline-bitline coupling ratio below 50%. The sensing scheme also achieves an intelligent page copy function with 20% reduction in time and without external buffers and CPU resources.
ER -
English
