Couplers in a film-type capacitive wireless power charging (CWC) system for an implantable medical device were designed and analyzed in this work. Due to the high conductivity of the human body, two paths contribute to the power transmission, namely a high-frequency current and an electric field. This was confirmed by an equivalent circuit of the system. During analysis of the system, we used pig skin with subcutaneous fat, which has a high affinity with the human body, to search for a highly efficient electrode shape. Subsequently, we fabricated the designed coupler and measured ηmax. An ηmax of 56.6% was obtained for a half-circular coupler with a radius of 20 mm and a distance of 10 mm between adjacent couplers. This study will contribute to the realization of implantable devices that can be recharged during breaks or while sleeping at home and is expected to significantly reduce the burden on patients.

Coil-shaped structures are proposed to enhance sensitivity and spatial resolution for EMI near-field probe. This design yields a high sensitivity and a good spatial resolution to find the EMI source in near-field region. Both characteristics are crucial to diagnosis of emissions from electrical and electronic devices. The new design yields a superior sensitivity, which is in general 15 dB greater than conventional probes. This new probe helps practitioners to quickly and correctly locate noise emission source areas on printed circuit boards and devices. Two prototypes of different sizes were fabricated. The larger one provides a high sensitivity while the smaller one can pinpoint emission source locations. The new probe design also has an orientation invariance feature. Its noise response levels are similar for all probe directions. This characteristic can help reduced the probability at miss-detection since sensitivity is largely invariant to its orientation. Extensive measurements were performed to verify the operation mechanism and to assess probe characteristics. It suits well to the electromagnetic interference problem diagnosis.

A capacitive coupling wireless connector circuit is implemented with 50 µm 50 µm pads, which is a 25X reduction of pad size compared with previous wireless connectors by allowing contacting and non-contacting modes. The proposed track and charge scheme allows both contacting and non-contacting communication through PCB capacitive pads. By making the precharge level of the input VDD or VSS, instead of 1/2 VDD, the time necessary to precharge is reduced. The proposed digitally tunable comparator does not require analog voltages, reduces the power to less than 1/20 at lower frequencies compared to previous capacitive coupling receivers. A test chip successfully transmitted and received 1 Gb/s, 27-1PRBS signal at 1 mW while increasing design freedom of the wireless connectors.

This paper describes a capacitive voltage probe (CVP) that can measure a common-mode voltage on a cable without touching its conductor. This CVP has two coaxial electrodes: the inner electrode works as a voltage pickup and the outer one shields the inner electrode. These electrodes separate into two parts for clamping to the cable. Using a high input impedance circuit, this probe measures the common-mode voltage by detecting the voltage difference between the two electrodes. The probe characteristics are evaluated by measuring its linearity and frequency response. The results show that this probe has a dynamic range of 100 dB and flat frequency response from 10 kHz to 30 MHz. Deviations in sensitivity due to the position of the clamped cable in the inner electrode and to differences in the cable radius are evaluated theoretically and experimentally. The results indicate that the influence of the cable position can be calibrated. Finally, measured data obtained using both an impedance stabilizing network (ISN) and a CVP are compared to confirm the validity of the CVP. The results show that data measured by the CVP closely agreed with that obtained by the ISN. Therefore, the CVP is useful for EMC measurements to evaluate common-mode disturbances.

This paper proposes a post-layout transistor sizing method for crosstalk noise reduction. The proposed method downsizes the drivers of aggressor wires for noise reduction, utilizing the precise interconnect information extracted from the detail-routed layouts. We develop a transistor sizing algorithm for crosstalk noise reduction under delay constraints, and construct a crosstalk noise optimization method utilizing an analytic crosstalk noise model and a transistor sizing framework that have been developed. Our method exploits the transistor sizing framework that can vary transistor widths inside cells with interconnects unchanged. Our optimization method therefore never causes a new crosstalk noise problem, and does not need iterative layout optimization. The effectiveness of the proposed method is experimentally examined using 2 circuits. The maximum noise voltage is reduced by more than 50% without delay violation. These results show that the risk of crosstalk noise problems can be considerably reduced after detail-routing.

We propose an estimation method of crosstalk noise for generic RC trees. The proposed method derives an analytic waveform of crosstalk noise in a 2-π equivalent circuit. The peak voltage is calculated from the closed-form expression. We also develop a transformation method from generic RC trees with branches into the 2-π model circuit. The proposed method can hence estimate crosstalk noise for any RC trees. Our estimation method is evaluated in a 0.13 µm technology. The peak noise of two partially-coupled interconnects is estimated with the average error of 11%. Our method transforms generic RC interconnects with branches into the 2-π model with 14% error on average.

In this study, the influence of the location of ground plane on the noise (crosstalk) induced on twisted-pair-wire (TPW) by parallel wire is experimentally and theoretically discussed by paying attention to the capacitive coupling between TPW and parallel wire. The capacitance is obtained by applying the finite element method (FEM) to the calculation of electric field intensity. It is confirmed that the calculated results are in good agreement with the experimental results within 0.5 dB. It is concluded that the closer the TPW is to the ground plane, the smaller the induced noise on the TPW becomes.

This paper describes a newly developed sensing scheme with a bit-by-bit program verify technique for NAND flash disk systems. This sensing scheme achieves good noise immunity for large capacitive coupling between bitlines, and makes NAND flash memories operable for flexible power supply voltages including both 3.3V and 5V. A highly reliable read operation is performed for power supply voltages above 3V and a bitline-bitline coupling ratio below 50%. The sensing scheme also achieves an intelligent page copy function with 20% reduction in time and without external buffers and CPU resources.

This paper discusses multiple-valued memory circuit using floating gate devices. It is an object of the paper to provide a new and improved analog memory device, which permits the memory of an amount of charges that accurately corresponds to analog information to be stored.