IEICE TRANSACTIONS on Fundamentals
Crosstalk Noise Optimization by Post-Layout Transistor Sizing
Summary :
This paper proposes a post-layout transistor sizing method for crosstalk noise reduction. The proposed method downsizes the drivers of aggressor wires for noise reduction, utilizing the precise interconnect information extracted from the detail-routed layouts. We develop a transistor sizing algorithm for crosstalk noise reduction under delay constraints, and construct a crosstalk noise optimization method utilizing an analytic crosstalk noise model and a transistor sizing framework that have been developed. Our method exploits the transistor sizing framework that can vary transistor widths inside cells with interconnects unchanged. Our optimization method therefore never causes a new crosstalk noise problem, and does not need iterative layout optimization. The effectiveness of the proposed method is experimentally examined using 2 circuits. The maximum noise voltage is reduced by more than 50% without delay violation. These results show that the risk of crosstalk noise problems can be considerably reduced after detail-routing.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.12 pp.3251-3257
- Publication Date
- 2004/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Physical Design
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Keyword
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Masanori HASHIMOTO, Hidetoshi ONODERA, "Crosstalk Noise Optimization by Post-Layout Transistor Sizing" in IEICE TRANSACTIONS on Fundamentals,
vol. E87-A, no. 12, pp. 3251-3257, December 2004, doi: .
Abstract: This paper proposes a post-layout transistor sizing method for crosstalk noise reduction. The proposed method downsizes the drivers of aggressor wires for noise reduction, utilizing the precise interconnect information extracted from the detail-routed layouts. We develop a transistor sizing algorithm for crosstalk noise reduction under delay constraints, and construct a crosstalk noise optimization method utilizing an analytic crosstalk noise model and a transistor sizing framework that have been developed. Our method exploits the transistor sizing framework that can vary transistor widths inside cells with interconnects unchanged. Our optimization method therefore never causes a new crosstalk noise problem, and does not need iterative layout optimization. The effectiveness of the proposed method is experimentally examined using 2 circuits. The maximum noise voltage is reduced by more than 50% without delay violation. These results show that the risk of crosstalk noise problems can be considerably reduced after detail-routing.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_12_3251/_p
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@ARTICLE{e87-a_12_3251,
author={Masanori HASHIMOTO, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Crosstalk Noise Optimization by Post-Layout Transistor Sizing},
year={2004},
volume={E87-A},
number={12},
pages={3251-3257},
abstract={This paper proposes a post-layout transistor sizing method for crosstalk noise reduction. The proposed method downsizes the drivers of aggressor wires for noise reduction, utilizing the precise interconnect information extracted from the detail-routed layouts. We develop a transistor sizing algorithm for crosstalk noise reduction under delay constraints, and construct a crosstalk noise optimization method utilizing an analytic crosstalk noise model and a transistor sizing framework that have been developed. Our method exploits the transistor sizing framework that can vary transistor widths inside cells with interconnects unchanged. Our optimization method therefore never causes a new crosstalk noise problem, and does not need iterative layout optimization. The effectiveness of the proposed method is experimentally examined using 2 circuits. The maximum noise voltage is reduced by more than 50% without delay violation. These results show that the risk of crosstalk noise problems can be considerably reduced after detail-routing.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Crosstalk Noise Optimization by Post-Layout Transistor Sizing
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3251
EP - 3257
AU - Masanori HASHIMOTO
AU - Hidetoshi ONODERA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2004
AB - This paper proposes a post-layout transistor sizing method for crosstalk noise reduction. The proposed method downsizes the drivers of aggressor wires for noise reduction, utilizing the precise interconnect information extracted from the detail-routed layouts. We develop a transistor sizing algorithm for crosstalk noise reduction under delay constraints, and construct a crosstalk noise optimization method utilizing an analytic crosstalk noise model and a transistor sizing framework that have been developed. Our method exploits the transistor sizing framework that can vary transistor widths inside cells with interconnects unchanged. Our optimization method therefore never causes a new crosstalk noise problem, and does not need iterative layout optimization. The effectiveness of the proposed method is experimentally examined using 2 circuits. The maximum noise voltage is reduced by more than 50% without delay violation. These results show that the risk of crosstalk noise problems can be considerably reduced after detail-routing.
ER -
English
