This paper describes a newly developed sensing scheme with a bit-by-bit program verify technique for NAND flash disk systems. This sensing scheme achieves good noise immunity for large capacitive coupling between bitlines, and makes NAND flash memories operable for flexible power supply voltages including both 3.3V and 5V. A highly reliable read operation is performed for power supply voltages above 3V and a bitline-bitline coupling ratio below 50%. The sensing scheme also achieves an intelligent page copy function with 20% reduction in time and without external buffers and CPU resources.

The method to optimize redundancy scheme for memory devices is proposed. Yield for new generation memories is predicted by failure mode analysis of previous generation memories. Fabrication line improvement and chip area penalty by the redundancy are taken into account for this yield prediction. The actual data of 16 Mbit EPROM failure analysis indicate the effectiveness of the prediction.