Statistical Memory Yield Analysis and Redundancy Design Considering Fabrication Line Improvement
Summary :
The method to optimize redundancy scheme for memory devices is proposed. Yield for new generation memories is predicted by failure mode analysis of previous generation memories. Fabrication line improvement and chip area penalty by the redundancy are taken into account for this yield prediction. The actual data of 16 Mbit EPROM failure analysis indicate the effectiveness of the prediction.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E76-C No.11 pp.1626-1631
- Publication Date
- 1993/11/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on LSI Memories)
- Category
- Non-volatile Memory
Authors
Keyword
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Ken-ichi IMAMIYA, Jun-ichi MIYAMOTO, Nobuaki OHTSUKA, Naoto TOMITA, Yumiko IYAMA, "Statistical Memory Yield Analysis and Redundancy Design Considering Fabrication Line Improvement" in IEICE TRANSACTIONS on Electronics,
vol. E76-C, no. 11, pp. 1626-1631, November 1993, doi: .
Abstract: The method to optimize redundancy scheme for memory devices is proposed. Yield for new generation memories is predicted by failure mode analysis of previous generation memories. Fabrication line improvement and chip area penalty by the redundancy are taken into account for this yield prediction. The actual data of 16 Mbit EPROM failure analysis indicate the effectiveness of the prediction.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_11_1626/_p
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@ARTICLE{e76-c_11_1626,
author={Ken-ichi IMAMIYA, Jun-ichi MIYAMOTO, Nobuaki OHTSUKA, Naoto TOMITA, Yumiko IYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Statistical Memory Yield Analysis and Redundancy Design Considering Fabrication Line Improvement},
year={1993},
volume={E76-C},
number={11},
pages={1626-1631},
abstract={The method to optimize redundancy scheme for memory devices is proposed. Yield for new generation memories is predicted by failure mode analysis of previous generation memories. Fabrication line improvement and chip area penalty by the redundancy are taken into account for this yield prediction. The actual data of 16 Mbit EPROM failure analysis indicate the effectiveness of the prediction.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Statistical Memory Yield Analysis and Redundancy Design Considering Fabrication Line Improvement
T2 - IEICE TRANSACTIONS on Electronics
SP - 1626
EP - 1631
AU - Ken-ichi IMAMIYA
AU - Jun-ichi MIYAMOTO
AU - Nobuaki OHTSUKA
AU - Naoto TOMITA
AU - Yumiko IYAMA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1993
AB - The method to optimize redundancy scheme for memory devices is proposed. Yield for new generation memories is predicted by failure mode analysis of previous generation memories. Fabrication line improvement and chip area penalty by the redundancy are taken into account for this yield prediction. The actual data of 16 Mbit EPROM failure analysis indicate the effectiveness of the prediction.
ER -
English
