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Ken-ichi IMAMIYA Jun-ichi MIYAMOTO Nobuaki OHTSUKA Naoto TOMITA Yumiko IYAMA
The method to optimize redundancy scheme for memory devices is proposed. Yield for new generation memories is predicted by failure mode analysis of previous generation memories. Fabrication line improvement and chip area penalty by the redundancy are taken into account for this yield prediction. The actual data of 16 Mbit EPROM failure analysis indicate the effectiveness of the prediction.