IEICE TRANSACTIONS on Electronics
2V/120 ns Embedded Flash EEPROM Circuit Technology
Summary :
A 2V/120 ns flash EEPROM embedded in a microcontroller has been fabricated in 0.8 µm double-metal CMOS process technology with a simple stacked gate memory cell. To achieve low voltage and high speed operation, novel circuit technology and architecture; (a) PMOS-precharging NMOS-self-boost word line circuit with a higher voltage selector, (b) new erase algorithm for reverse operation, (c) column gate boost circuit, (d) hard-verify mode for replacing weak cells, (e) efficient redundancy of row and column lines, have been developed. A 512 kb flash EEPROM core chip incorporating these circuit techniques and architecture operate at 1.8 V and accesses data in 120 ns at 2 V and 70
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E79-C No.6 pp.825-831
- Publication Date
- 1996/06/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on ULSI Memory Technology)
- Category
- Nonvolatile memories
Authors
Keyword
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Horoshige HIRANO, Toshiyuki HONDA, Shigeo CHAYA, Takahiro FUKUMOTO, Tatsumi SUMI, "2V/120 ns Embedded Flash EEPROM Circuit Technology" in IEICE TRANSACTIONS on Electronics,
vol. E79-C, no. 6, pp. 825-831, June 1996, doi: .
Abstract: A 2V/120 ns flash EEPROM embedded in a microcontroller has been fabricated in 0.8 µm double-metal CMOS process technology with a simple stacked gate memory cell. To achieve low voltage and high speed operation, novel circuit technology and architecture; (a) PMOS-precharging NMOS-self-boost word line circuit with a higher voltage selector, (b) new erase algorithm for reverse operation, (c) column gate boost circuit, (d) hard-verify mode for replacing weak cells, (e) efficient redundancy of row and column lines, have been developed. A 512 kb flash EEPROM core chip incorporating these circuit techniques and architecture operate at 1.8 V and accesses data in 120 ns at 2 V and 70
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_6_825/_p
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@ARTICLE{e79-c_6_825,
author={Horoshige HIRANO, Toshiyuki HONDA, Shigeo CHAYA, Takahiro FUKUMOTO, Tatsumi SUMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={2V/120 ns Embedded Flash EEPROM Circuit Technology},
year={1996},
volume={E79-C},
number={6},
pages={825-831},
abstract={A 2V/120 ns flash EEPROM embedded in a microcontroller has been fabricated in 0.8 µm double-metal CMOS process technology with a simple stacked gate memory cell. To achieve low voltage and high speed operation, novel circuit technology and architecture; (a) PMOS-precharging NMOS-self-boost word line circuit with a higher voltage selector, (b) new erase algorithm for reverse operation, (c) column gate boost circuit, (d) hard-verify mode for replacing weak cells, (e) efficient redundancy of row and column lines, have been developed. A 512 kb flash EEPROM core chip incorporating these circuit techniques and architecture operate at 1.8 V and accesses data in 120 ns at 2 V and 70
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - 2V/120 ns Embedded Flash EEPROM Circuit Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 825
EP - 831
AU - Horoshige HIRANO
AU - Toshiyuki HONDA
AU - Shigeo CHAYA
AU - Takahiro FUKUMOTO
AU - Tatsumi SUMI
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1996
AB - A 2V/120 ns flash EEPROM embedded in a microcontroller has been fabricated in 0.8 µm double-metal CMOS process technology with a simple stacked gate memory cell. To achieve low voltage and high speed operation, novel circuit technology and architecture; (a) PMOS-precharging NMOS-self-boost word line circuit with a higher voltage selector, (b) new erase algorithm for reverse operation, (c) column gate boost circuit, (d) hard-verify mode for replacing weak cells, (e) efficient redundancy of row and column lines, have been developed. A 512 kb flash EEPROM core chip incorporating these circuit techniques and architecture operate at 1.8 V and accesses data in 120 ns at 2 V and 70
ER -
English
