Special and Embedded Memory Macrocells for Low-Cost and Low-Power in MPEG Environment

Hiroyuki HARA; Masataka MATSUI; Goichi OTOMO; Katsuhiro SETA; Takayasu SAKURAI

Special and Embedded Memory Macrocells for Low-Cost and Low-Power in MPEG Environment

Hiroyuki HARA, Masataka MATSUI, Goichi OTOMO, Katsuhiro SETA, Takayasu SAKURAI

Full Text Views

0

Cite this

Summary :

Special memory and embedded memories used in a newly designed MPEG2 decorder LSI are described. Orthogonal memory, which has a functionality of parallel-to-serial transposition, is employed in a IDCT(Inverse Discrete Cosine Transform) block for small area and low-power. The orthogonal memory realizes the special pupose with 50% of the area and the power compared with using flip-flop array. FIFO's and other dual-port memories are designed by using a single-port RAM operated twice in one clock cycle to reduce cost. Flip-Flop cell is one of the important memory elements in the MPEG environment, and is also improved for the low-cost optimizing functionality for video processing. The area and power of the fabricated MPEG2 decoder chip are reduced by 20% using these techniques. As for testability, direct test mode is implemented for small area. An instruction RAM is placed outside the pad area in parallel to a normal instruction ROM and activated by Al-masterslice for extensive debugging and an early sampling. Other memory related techniques and the key features of the decoder LSI are also described.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.6 pp.750-756

Publication Date: 1996/06/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology)

Category: Static RAMs

Cite this

Copy

Hiroyuki HARA, Masataka MATSUI, Goichi OTOMO, Katsuhiro SETA, Takayasu SAKURAI, "Special and Embedded Memory Macrocells for Low-Cost and Low-Power in MPEG Environment" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 6, pp. 750-756, June 1996, doi: .
Abstract: Special memory and embedded memories used in a newly designed MPEG2 decorder LSI are described. Orthogonal memory, which has a functionality of parallel-to-serial transposition, is employed in a IDCT(Inverse Discrete Cosine Transform) block for small area and low-power. The orthogonal memory realizes the special pupose with 50% of the area and the power compared with using flip-flop array. FIFO's and other dual-port memories are designed by using a single-port RAM operated twice in one clock cycle to reduce cost. Flip-Flop cell is one of the important memory elements in the MPEG environment, and is also improved for the low-cost optimizing functionality for video processing. The area and power of the fabricated MPEG2 decoder chip are reduced by 20% using these techniques. As for testability, direct test mode is implemented for small area. An instruction RAM is placed outside the pad area in parallel to a normal instruction ROM and activated by Al-masterslice for extensive debugging and an early sampling. Other memory related techniques and the key features of the decoder LSI are also described.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_6_750/_p

Copy

@ARTICLE{e79-c_6_750,
author={Hiroyuki HARA, Masataka MATSUI, Goichi OTOMO, Katsuhiro SETA, Takayasu SAKURAI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Special and Embedded Memory Macrocells for Low-Cost and Low-Power in MPEG Environment},
year={1996},
volume={E79-C},
number={6},
pages={750-756},
abstract={Special memory and embedded memories used in a newly designed MPEG2 decorder LSI are described. Orthogonal memory, which has a functionality of parallel-to-serial transposition, is employed in a IDCT(Inverse Discrete Cosine Transform) block for small area and low-power. The orthogonal memory realizes the special pupose with 50% of the area and the power compared with using flip-flop array. FIFO's and other dual-port memories are designed by using a single-port RAM operated twice in one clock cycle to reduce cost. Flip-Flop cell is one of the important memory elements in the MPEG environment, and is also improved for the low-cost optimizing functionality for video processing. The area and power of the fabricated MPEG2 decoder chip are reduced by 20% using these techniques. As for testability, direct test mode is implemented for small area. An instruction RAM is placed outside the pad area in parallel to a normal instruction ROM and activated by Al-masterslice for extensive debugging and an early sampling. Other memory related techniques and the key features of the decoder LSI are also described.},
keywords={},
doi={},
ISSN={},
month={June},}

Copy

TY - JOUR
TI - Special and Embedded Memory Macrocells for Low-Cost and Low-Power in MPEG Environment
T2 - IEICE TRANSACTIONS on Electronics
SP - 750
EP - 756
AU - Hiroyuki HARA
AU - Masataka MATSUI
AU - Goichi OTOMO
AU - Katsuhiro SETA
AU - Takayasu SAKURAI
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1996
AB - Special memory and embedded memories used in a newly designed MPEG2 decorder LSI are described. Orthogonal memory, which has a functionality of parallel-to-serial transposition, is employed in a IDCT(Inverse Discrete Cosine Transform) block for small area and low-power. The orthogonal memory realizes the special pupose with 50% of the area and the power compared with using flip-flop array. FIFO's and other dual-port memories are designed by using a single-port RAM operated twice in one clock cycle to reduce cost. Flip-Flop cell is one of the important memory elements in the MPEG environment, and is also improved for the low-cost optimizing functionality for video processing. The area and power of the fabricated MPEG2 decoder chip are reduced by 20% using these techniques. As for testability, direct test mode is implemented for small area. An instruction RAM is placed outside the pad area in parallel to a normal instruction ROM and activated by Al-masterslice for extensive debugging and an early sampling. Other memory related techniques and the key features of the decoder LSI are also described.
ER -