A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories
Summary :
To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E75-C No.4 pp.481-486
- Publication Date
- 1992/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
- Category
Authors
Yoshikazu MIYAWAKI
Takeshi NAKAYAMA
Shin-ichi KOBAYASHI
Natsuo AJIKA
Makoto OHI
Yasushi TERADA
Hideaki ARIMA
Tsutomu YOSHIHARA
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Yoshikazu MIYAWAKI, Takeshi NAKAYAMA, Shin-ichi KOBAYASHI, Natsuo AJIKA, Makoto OHI, Yasushi TERADA, Hideaki ARIMA, Tsutomu YOSHIHARA, "A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories" in IEICE TRANSACTIONS on Electronics,
vol. E75-C, no. 4, pp. 481-486, April 1992, doi: .
Abstract: To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_4_481/_p
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@ARTICLE{e75-c_4_481,
author={Yoshikazu MIYAWAKI, Takeshi NAKAYAMA, Shin-ichi KOBAYASHI, Natsuo AJIKA, Makoto OHI, Yasushi TERADA, Hideaki ARIMA, Tsutomu YOSHIHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories},
year={1992},
volume={E75-C},
number={4},
pages={481-486},
abstract={To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories
T2 - IEICE TRANSACTIONS on Electronics
SP - 481
EP - 486
AU - Yoshikazu MIYAWAKI
AU - Takeshi NAKAYAMA
AU - Shin-ichi KOBAYASHI
AU - Natsuo AJIKA
AU - Makoto OHI
AU - Yasushi TERADA
AU - Hideaki ARIMA
AU - Tsutomu YOSHIHARA
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1992
AB - To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.
ER -
English
