This paper proposes the tile size conversion method for the wavelet image transcoding gateway and a set of methods to reduce the tile boundary artifacts caused by the conversion. In the wavelet image coding system represented by JPEG 2000, pictures are usually divided into one or more tiles and each tile is then transformed separately. On low memory terminals such as mobile terminals, some decoders are likely to have limits on what tile sizes they can decode. Assuming a system using these limited decoders, methods were investigated for converting the tile size quickly and automatically at the gateway when image data with a non-decodable tile size is received at the gateway from another system. Furthermore, tile boundary artifacts reduction methods are investigated. This paper verifies the validity of the proposed scheme by implementing it with a (5, 3) reversible filter and a (9, 7) irreversible filter. In addition, we implemented the tile size conversion gateway and evaluated the performance of the processing time. The results show the validity of the conversion gateway.

This paper proposes an effective JPEG 2000 encoding method for reducing tiling artifacts, which cause one of the biggest problems in JPEG 2000 encoders. Symmetric pixel extension is generally thought to be the main factor in causing artifacts. However this paper shows that differences in quantization accuracy between tiles are a more significant reason for tiling artifacts at middle or low bit rates. This paper also proposes an algorithm that predicts whether tiling artifacts will occur at a tile boundary in the rate control process and that locally improves quantization accuracy by the original post quantization control. This paper further proposes a method for reducing processing time which is yet another serious problem in the JPEG 2000 encoder. The method works by predicting truncation points using the entropy of wavelet transform coefficients prior to the arithmetic coding. These encoding methods require no additional processing in the decoder. The experiments confirmed that tiling artifacts were greatly reduced and that the coding process was considerably accelerated.

This paper describes a new biasing scheme for sensing circuits, namely an automated bias control (ABC) circuit, for high-performance VLSI's. The ABC circuit can automatically gear the output level of sensing circuits to the input threshold voltage of the succeeding CMOS converters. The sensing performance can be accelerated with the ABC circuit either by reducing excessive signal level margin between the sensing circuits and the CMOS converters or by reducing extra stage of signal amplification. Since feedback control of the ABC circuit ensures a correct dc biasing even under large process deviation and circuit condition changes, wider operation margin can also be obtained. Three successful applications of the ABC circuit are reported: a sense amplifier, an address transition detector (ATD), and an ECL-CMOS input buffer. A 64-kb BiCMOS SRAM employing the proposed sense amplifier and the ATD has been fabricated with a 0.8-µm 9-GHz BiCMOS technology. The SRAM has an address access time of 4.5 ns.