1-3hit |
Tadahiro KURODA Toshiyuki FUKUNAGA Kenji MATSUO Kazuhiko KASAI Ayako HIRATA Shinji FUJII Masahiro KIMURA Hiroaki SUZUKI
This paper describes a new biasing scheme for sensing circuits, namely an automated bias control (ABC) circuit, for high-performance VLSI's. The ABC circuit can automatically gear the output level of sensing circuits to the input threshold voltage of the succeeding CMOS converters. The sensing performance can be accelerated with the ABC circuit either by reducing excessive signal level margin between the sensing circuits and the CMOS converters or by reducing extra stage of signal amplification. Since feedback control of the ABC circuit ensures a correct dc biasing even under large process deviation and circuit condition changes, wider operation margin can also be obtained. Three successful applications of the ABC circuit are reported: a sense amplifier, an address transition detector (ATD), and an ECL-CMOS input buffer. A 64-kb BiCMOS SRAM employing the proposed sense amplifier and the ATD has been fabricated with a 0.8-µm 9-GHz BiCMOS technology. The SRAM has an address access time of 4.5 ns.
Minoru ASADA Masahiro KIMURA Yoshiaki SHIRAI
Integration of 2
Hiroji KUSAKA Toshihisa NAKAI Masahiro KIMURA Tetsuya NIINO
A narrowband interference in direct sequence spread spectrum communication systems also affects the characteristics of a delay lock loop. In this paper, the delay errors of a baseband delay lock loop (DLL) in the presence of the interference which consists of a narrowband Gaussian noise and several tones are examined, and when a filter is used to reject the interference, the characteristics of the DLL are analyzed using the Fourier method. Furthermore, from the calculation results of the delay error in case where a prediction error filter with two-sided taps is used as the rejection filter, it is shown that the filter is necessary to keep the DLL in the lock-on state.