Analog switched-capacitor memory circuits are suitable for use in a wide range of applications where analog waveforms must be captured or delayed, such as the recording of pulse echo events and pulse shapes. Analog sampling systems based on switched-capacitor techniques offer performance superior to that of flash A/D converters and charge-coupled devices with respect to cost, density, dynamic range, sampling speed, and power consumption. This paper proposes an architecture with which sampling frequencies of several hundred megahertz can be achieved using conventional CMOS technology. Issues concerning the design and implementation of an analog memory circuit based on the proposed architecture are presented. An experimental two-channel memory with 32 sampling cells in each channel has been integrated in a 2-µm CMOS technology with poly-to-poly capacitors. The measured nonlinearity of this prototype is 0.03% for a 2.5 V input range, and the memory cell gain matching is 0.01% rms. The dynamic range of the memory exceeds 12 b for a sampling frequency of 700 MHz. The power dissipation for one channel operated from a single 5 V supply is 2 mW.

Switching transients in digital MOS circuits can perturb analog circuits integrated on the same die by means of coupling through the substrate. This paper describes an experimental technique for observing the effects of such substrate noise. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprised of an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is more effective than either physical separation or guard rings in minimizing substrate crosstalk between analog and digital circuits fabricated on epitaxial substrates. To enhance understanding of the experimental results, two-dimensional device simulations are used to show how crosstalk propagates via the heavily doped bulk. Device simulations are also used to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. Finally, a method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates has been developed using a single-node substrate model.