Conventionally, ultrahigh-speed 2:1 multiplexers and 1:2 demultiplexers have been demonstrated with HBT's, MESFET's, and Si BJT's. Multiplexers and demultiplexers with a high number of bits are desirable to simplify a system. An 8:1 multiplexer and a 1:8 demultiplexer operating at 6 Gb/s and a 16:1 multiplexer and a 1:16 demultiplexer operating at 10 Gb/s were realized by HBT's and MESFET's, respectively. This paper describes Si bipolar circuits and package design technology for a 5-Gb/s 8:1 multiplexer and a 4.2-Gb/s demultiplexer. These multigigabit LSI's have been mainly achieved by switching current optimization within the limit of keeping a maximum unity unilateral gain frequency (fmax), by careful circuit and layout design considering accurate parasitic capacitance modeling, and by using a high-speed Si bipolar technology. These LSI's are housed in a newly developed 56-pin six-layer ceramic package with chip resistors for ECL termination and chip capacitors for good RF grounding.