IEICE TRANSACTIONS on Electronics
A 1.7-V Adjustable I/O Interface for Low-Voltage Fast SRAM's
Summary :
An all-CMOS output buffer has been developed. The output buffer is composed of a voltage-follower and a source-follower circuit. The performance of the output buffer is characterized by a low-voltage operation of 1.7 V, a short delay of 1 ns, availability for the wired-OR connection, and adjustability to TTL, ECL, and a reduced swing level (RSL). The output buffer is incorporated into a 64-kb CMOS SRAM. This SRAM has achieved an access time of 4.3 ns at a supply voltage of -3.6 V.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E75-C No.4 pp.572-575
- Publication Date
- 1992/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
- Category
Authors
Keyword
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Koichiro ISHIBASHI, Katsuro SASAKI, Toshiaki YAMANAKA, Hiroshi TOYOSHIMA, Fumio KOJIMA, "A 1.7-V Adjustable I/O Interface for Low-Voltage Fast SRAM's" in IEICE TRANSACTIONS on Electronics,
vol. E75-C, no. 4, pp. 572-575, April 1992, doi: .
Abstract: An all-CMOS output buffer has been developed. The output buffer is composed of a voltage-follower and a source-follower circuit. The performance of the output buffer is characterized by a low-voltage operation of 1.7 V, a short delay of 1 ns, availability for the wired-OR connection, and adjustability to TTL, ECL, and a reduced swing level (RSL). The output buffer is incorporated into a 64-kb CMOS SRAM. This SRAM has achieved an access time of 4.3 ns at a supply voltage of -3.6 V.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_4_572/_p
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@ARTICLE{e75-c_4_572,
author={Koichiro ISHIBASHI, Katsuro SASAKI, Toshiaki YAMANAKA, Hiroshi TOYOSHIMA, Fumio KOJIMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 1.7-V Adjustable I/O Interface for Low-Voltage Fast SRAM's},
year={1992},
volume={E75-C},
number={4},
pages={572-575},
abstract={An all-CMOS output buffer has been developed. The output buffer is composed of a voltage-follower and a source-follower circuit. The performance of the output buffer is characterized by a low-voltage operation of 1.7 V, a short delay of 1 ns, availability for the wired-OR connection, and adjustability to TTL, ECL, and a reduced swing level (RSL). The output buffer is incorporated into a 64-kb CMOS SRAM. This SRAM has achieved an access time of 4.3 ns at a supply voltage of -3.6 V.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - A 1.7-V Adjustable I/O Interface for Low-Voltage Fast SRAM's
T2 - IEICE TRANSACTIONS on Electronics
SP - 572
EP - 575
AU - Koichiro ISHIBASHI
AU - Katsuro SASAKI
AU - Toshiaki YAMANAKA
AU - Hiroshi TOYOSHIMA
AU - Fumio KOJIMA
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1992
AB - An all-CMOS output buffer has been developed. The output buffer is composed of a voltage-follower and a source-follower circuit. The performance of the output buffer is characterized by a low-voltage operation of 1.7 V, a short delay of 1 ns, availability for the wired-OR connection, and adjustability to TTL, ECL, and a reduced swing level (RSL). The output buffer is incorporated into a 64-kb CMOS SRAM. This SRAM has achieved an access time of 4.3 ns at a supply voltage of -3.6 V.
ER -
English
