A 16-Mb CMOS SRAM using 0.4-µm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm2 is fabricated and an address access time of 12.5 ns has been achieved.

An all-CMOS output buffer has been developed. The output buffer is composed of a voltage-follower and a source-follower circuit. The performance of the output buffer is characterized by a low-voltage operation of 1.7 V, a short delay of 1 ns, availability for the wired-OR connection, and adjustability to TTL, ECL, and a reduced swing level (RSL). The output buffer is incorporated into a 64-kb CMOS SRAM. This SRAM has achieved an access time of 4.3 ns at a supply voltage of -3.6 V.