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Hideharu YAHATA Yoji NISHIO Kunihiro KOMIYAJI Hiroshi TOYOSHIMA Atsushi HIRAISHI Yoshitaka KINOSHITA
A 167-MHz 1-Mbit CMOS synchronous cache SRAM was developed using 0.40-µm process technology. The floor plan was designed so that the address registers are located in the center of the chip, and high-speed circuits were developed such as the quasi latch (QL) sense amplifier and the one-shot control (OSC) output register. To maintain suitable setup and hold time margins, an equivalent margin (EM) design method was developed. 167-MHz operation was measured at a supply voltage of 2.5 V and an ambient temperature of 75. The same margins 1.1 ns of the setup time and hold time were measured for the specifications of a setup time of 2.0 ns and a hold time of 0.5 ns.
Koichiro ISHIBASHI Koichi TAKASUGI Kunihiro KOMIYAJI Hiroshi TOYOSHIMA Toshiaki YAMANAKA Akira FUKAMI Naotaka HASHIMOTO Nagatoshi OHKI Akihiro SHIMIZU Takashi HASHIMOTO Takahiro NAGANO Takashi NISHIDA
A 4-Mb CMOS SRAM with 3.84 µm2 TFT load cells is fabricated using 0.25-µm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells.
Koichiro ISHIBASHI Kunihiro KOMIYAJI Sadayuki MORITA Toshiro AOTO Shuji IKEDA Kyoichiro ASAYAMA Atsuyosi KOIKE Toshiaki YAMANAKA Naotaka HASHIMOTO Haruhito IIDA Fumio KOJIMA Koichi MOTOHASHI Katsuro SASAKI
A 16-Mb CMOS SRAM using 0.4-µm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm2 is fabricated and an address access time of 12.5 ns has been achieved.