A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers
Summary :
A 16-Mb CMOS SRAM using 0.4-µm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm2 is fabricated and an address access time of 12.5 ns has been achieved.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E77-C No.5 pp.741-748
- Publication Date
- 1994/05/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- Category
Authors
Koichiro ISHIBASHI
Kunihiro KOMIYAJI
Sadayuki MORITA
Toshiro AOTO
Shuji IKEDA
Kyoichiro ASAYAMA
Atsuyosi KOIKE
Toshiaki YAMANAKA
Naotaka HASHIMOTO
Haruhito IIDA
Fumio KOJIMA
Koichi MOTOHASHI
Katsuro SASAKI
Keyword
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Koichiro ISHIBASHI, Kunihiro KOMIYAJI, Sadayuki MORITA, Toshiro AOTO, Shuji IKEDA, Kyoichiro ASAYAMA, Atsuyosi KOIKE, Toshiaki YAMANAKA, Naotaka HASHIMOTO, Haruhito IIDA, Fumio KOJIMA, Koichi MOTOHASHI, Katsuro SASAKI, "A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers" in IEICE TRANSACTIONS on Electronics,
vol. E77-C, no. 5, pp. 741-748, May 1994, doi: .
Abstract: A 16-Mb CMOS SRAM using 0.4-µm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm2 is fabricated and an address access time of 12.5 ns has been achieved.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_5_741/_p
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@ARTICLE{e77-c_5_741,
author={Koichiro ISHIBASHI, Kunihiro KOMIYAJI, Sadayuki MORITA, Toshiro AOTO, Shuji IKEDA, Kyoichiro ASAYAMA, Atsuyosi KOIKE, Toshiaki YAMANAKA, Naotaka HASHIMOTO, Haruhito IIDA, Fumio KOJIMA, Koichi MOTOHASHI, Katsuro SASAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers},
year={1994},
volume={E77-C},
number={5},
pages={741-748},
abstract={A 16-Mb CMOS SRAM using 0.4-µm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm2 is fabricated and an address access time of 12.5 ns has been achieved.},
keywords={},
doi={},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers
T2 - IEICE TRANSACTIONS on Electronics
SP - 741
EP - 748
AU - Koichiro ISHIBASHI
AU - Kunihiro KOMIYAJI
AU - Sadayuki MORITA
AU - Toshiro AOTO
AU - Shuji IKEDA
AU - Kyoichiro ASAYAMA
AU - Atsuyosi KOIKE
AU - Toshiaki YAMANAKA
AU - Naotaka HASHIMOTO
AU - Haruhito IIDA
AU - Fumio KOJIMA
AU - Koichi MOTOHASHI
AU - Katsuro SASAKI
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1994
AB - A 16-Mb CMOS SRAM using 0.4-µm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm2 is fabricated and an address access time of 12.5 ns has been achieved.
ER -
English
