A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM
Summary :
A 167-MHz 1-Mbit CMOS synchronous cache SRAM was developed using 0.40-µm process technology. The floor plan was designed so that the address registers are located in the center of the chip, and high-speed circuits were developed such as the quasi latch (QL) sense amplifier and the one-shot control (OSC) output register. To maintain suitable setup and hold time margins, an equivalent margin (EM) design method was developed. 167-MHz operation was measured at a supply voltage of 2.5 V and an ambient temperature of 75
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E80-C No.4 pp.557-565
- Publication Date
- 1997/04/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
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Hideharu YAHATA, Yoji NISHIO, Kunihiro KOMIYAJI, Hiroshi TOYOSHIMA, Atsushi HIRAISHI, Yoshitaka KINOSHITA, "A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM" in IEICE TRANSACTIONS on Electronics,
vol. E80-C, no. 4, pp. 557-565, April 1997, doi: .
Abstract: A 167-MHz 1-Mbit CMOS synchronous cache SRAM was developed using 0.40-µm process technology. The floor plan was designed so that the address registers are located in the center of the chip, and high-speed circuits were developed such as the quasi latch (QL) sense amplifier and the one-shot control (OSC) output register. To maintain suitable setup and hold time margins, an equivalent margin (EM) design method was developed. 167-MHz operation was measured at a supply voltage of 2.5 V and an ambient temperature of 75
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_4_557/_p
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@ARTICLE{e80-c_4_557,
author={Hideharu YAHATA, Yoji NISHIO, Kunihiro KOMIYAJI, Hiroshi TOYOSHIMA, Atsushi HIRAISHI, Yoshitaka KINOSHITA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM},
year={1997},
volume={E80-C},
number={4},
pages={557-565},
abstract={A 167-MHz 1-Mbit CMOS synchronous cache SRAM was developed using 0.40-µm process technology. The floor plan was designed so that the address registers are located in the center of the chip, and high-speed circuits were developed such as the quasi latch (QL) sense amplifier and the one-shot control (OSC) output register. To maintain suitable setup and hold time margins, an equivalent margin (EM) design method was developed. 167-MHz operation was measured at a supply voltage of 2.5 V and an ambient temperature of 75
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM
T2 - IEICE TRANSACTIONS on Electronics
SP - 557
EP - 565
AU - Hideharu YAHATA
AU - Yoji NISHIO
AU - Kunihiro KOMIYAJI
AU - Hiroshi TOYOSHIMA
AU - Atsushi HIRAISHI
AU - Yoshitaka KINOSHITA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1997
AB - A 167-MHz 1-Mbit CMOS synchronous cache SRAM was developed using 0.40-µm process technology. The floor plan was designed so that the address registers are located in the center of the chip, and high-speed circuits were developed such as the quasi latch (QL) sense amplifier and the one-shot control (OSC) output register. To maintain suitable setup and hold time margins, an equivalent margin (EM) design method was developed. 167-MHz operation was measured at a supply voltage of 2.5 V and an ambient temperature of 75
ER -
English
