A vibration-to-electric energy converter as a power generator through a variable-resonating capacitor is theoretically and experimentally demonstrated as a potential on-chip battery. The converter is constructed from three components: a mechanical-variable capacitor, a charge-transporter circuit and a timing-capture control circuit. An optimum design methodology is theoretically described to maximize the efficiency of the vibration-to-electric energy conversion. The energy-conversion efficiency is analyzed based on the following three factors: the mechanical-energy to electric-energy conversion loss, the parasitic elements loss in the charge-transporter circuit and the timing error in the timing-capture circuit. Through the mechanical-energy conversion analysis, the optimum condition for the resonance is found. The parasitic elements in the charge-transporter circuit and the timing management of the capture circuit dominate the output energy efficiency. These analyses enable the optimum design of the energy-conversion system. The converter is fabricated experimentally. The practical measured power is 0.12 µW, and the conversion efficiency is 21%. This efficiency is calculated from a 43% mechanical-energy conversion loss and a 63% charge-transportation loss. The timing-capture circuit is manually controlled in this experiment, so that the timing error is not considered in the efficiency. From our result, a new system LSI application with an embedded power source can be explored for the ubiquitous computing world.

A charge-integration read scheme has been developed for a solid-nanopore DNA-sequencer that determines a genome by direct and electrical measurements of transverse tunneling current in single-stranded DNA. The magnitude of the current was simulated with a first-principles molecular dynamics method. It was found that the magnitude is as small as in the sub-pico ampere range, and signals from four bases represent wide distributions with overlaps between each base. The distribution is believed to originate with translational and rotational motion of DNA in a nanopore with a frequency of over 105 Hz. A sequence scheme is presented to distinguish the distributed signals. The scheme makes widely distributed signals time-integrated convergent by cumulating charge at the capacitance of a nanopore device and read circuits. We estimated that an integration time of 1.4 ms is sufficient to obtain a signal difference of over 10 mV for distinguishing between each DNA base. Moreover, the time is shortened if paired bases, such as A-T and C-G in double-stranded DNA, can be measured simultaneously with two nanopores. Circuit simulations, which included the capacitance of a nanopore calculated with a device simulator, successfully distinguished between DNA bases in less than 2.0 ms. The speed is roughly six orders faster than that of a conventional DNA sequencer. It is possible to determine the human genome in one day if 100-nanopores are operated in parallel.

A 0.3-µm sub-10-ns ECL 4-Mb BiCMOS DRAM design is described. The results obtained are: 1) a Vcc connection limiter with a BiCMOS output circuit is chosen due to ease of design, excellent device reliability, and layout area; 2) a mostly CMOS periphery with a specific bipolar use provides better performances at high speed and low power; 3) the direct sensing scheme of a single-stage MOS preamplifier combined with a bipolar main amplifier offers high speed; and 4) the strict control of MOS transistor parameters has been proven to be more important in obtaining high speed-DRAM's, based on the 4-Mb design.

Two types of dynamic termination, latch-type and RC-type, are useful for low-power high-speed chip interconnection where the transmission line is terminated only if the signal is changed. The gate of the termination MOS in the latch-type is driven by a feedback inverter, and that in the RC-type is driven by a differentiating signal through the resistor and capacitor. The power dissipation is 13% for the latch-type, and 11% for the RC-type in a DC termination scheme, and the overshoot is 32% for the latch-type, and 16% for the RC-type in an open scheme, both at a signal amplitude of 2 V. The RC-type is superior for signal swing as low as a 1 V. On the other hand, RC termination requires large capacitance, and thus high power. Diode termination is not effective for a small swing because of the large ON voltage of diodes.

A DRAM-cell array with 12-F2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and read-out times of the twin-cell array are shorter than those of a single-cell array by 70% and 40% respectively, because of parallel writing and reading of half charge to and from two memory cells. According to measured retention characteristics of the single cells, the twin-cell array improves retention time by 20% compared with the single-cell array at 1 V and keeps the retention time of the single-cell array at 0.4 V. Furthermore, the cell accepts the plate-driven scheme without the need of a dummy cell, lowering the necessary word-line voltage by 0.4 V.

Low-voltage nanometer-scale embedded RAM cells are described. First, low-voltage RAM cells are compared in terms of cell size, threshold voltage for MOS transistor, and signal charge. Second, the solution for 6T and 4T SRAM cells to widen the voltage margin are investigated, especially the advantages with a back-gate controlled thin buried-oxide fully-depleted (FD) SOI are presented. Then, DRAM approach with a novel twin-cell is discussed in terms of improving the retention time and low-voltage operation. These low-voltage cell technologies are the promising candidates for future embedded RAMs.

In an IoT system, neural networks have the potential to perform advanced information processing in various environments. To clarify this, the robustness of a restricted Boltzmann machine (RBM) used for deep neural networks, such as a deep belief network (DBN), was studied in this paper. Even if memory or logic errors occurred in the circuit operating in the RBM while pre-training the DBN, they did not affect the identification rate of the DBN, showing the robustness of the RBM. In addition, robustness against soft errors was evaluated. The soft errors had almost no influence on the RBM unless they were as large as 1012 times or more in the 50-nm CMOS process.

We propose a Simulink model of a ring oscillator using saturating integrators. The oscillator's period is tuned via the saturation time of the integrators. Thus, timing jitters due to white and flicker noises are easily introduced into the model, enabling an efficient phase noise evaluation before transistor-level circuit design.