IEICE TRANSACTIONS on Electronics
Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation
Summary :
A DRAM-cell array with 12-F2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and read-out times of the twin-cell array are shorter than those of a single-cell array by 70% and 40% respectively, because of parallel writing and reading of half charge to and from two memory cells. According to measured retention characteristics of the single cells, the twin-cell array improves retention time by 20% compared with the single-cell array at 1 V and keeps the retention time of the single-cell array at 0.4 V. Furthermore, the cell accepts the plate-driven scheme without the need of a dummy cell, lowering the necessary word-line voltage by 0.4 V.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.758-764
- Publication Date
- 2007/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.4.758
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
- Category
- Memory
Authors
Riichiro TAKEMURA
Kiyoo ITOH
Tomonori SEKIGUCHI
Satoru AKIYAMA
Satoru HANZAWA
Kazuhiko KAJIGAYA
Takayuki KAWAHARA
Keyword
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Riichiro TAKEMURA, Kiyoo ITOH, Tomonori SEKIGUCHI, Satoru AKIYAMA, Satoru HANZAWA, Kazuhiko KAJIGAYA, Takayuki KAWAHARA, "Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 4, pp. 758-764, April 2007, doi: 10.1093/ietele/e90-c.4.758.
Abstract: A DRAM-cell array with 12-F2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and read-out times of the twin-cell array are shorter than those of a single-cell array by 70% and 40% respectively, because of parallel writing and reading of half charge to and from two memory cells. According to measured retention characteristics of the single cells, the twin-cell array improves retention time by 20% compared with the single-cell array at 1 V and keeps the retention time of the single-cell array at 0.4 V. Furthermore, the cell accepts the plate-driven scheme without the need of a dummy cell, lowering the necessary word-line voltage by 0.4 V.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.4.758/_p
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@ARTICLE{e90-c_4_758,
author={Riichiro TAKEMURA, Kiyoo ITOH, Tomonori SEKIGUCHI, Satoru AKIYAMA, Satoru HANZAWA, Kazuhiko KAJIGAYA, Takayuki KAWAHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation},
year={2007},
volume={E90-C},
number={4},
pages={758-764},
abstract={A DRAM-cell array with 12-F2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and read-out times of the twin-cell array are shorter than those of a single-cell array by 70% and 40% respectively, because of parallel writing and reading of half charge to and from two memory cells. According to measured retention characteristics of the single cells, the twin-cell array improves retention time by 20% compared with the single-cell array at 1 V and keeps the retention time of the single-cell array at 0.4 V. Furthermore, the cell accepts the plate-driven scheme without the need of a dummy cell, lowering the necessary word-line voltage by 0.4 V.},
keywords={},
doi={10.1093/ietele/e90-c.4.758},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation
T2 - IEICE TRANSACTIONS on Electronics
SP - 758
EP - 764
AU - Riichiro TAKEMURA
AU - Kiyoo ITOH
AU - Tomonori SEKIGUCHI
AU - Satoru AKIYAMA
AU - Satoru HANZAWA
AU - Kazuhiko KAJIGAYA
AU - Takayuki KAWAHARA
PY - 2007
DO - 10.1093/ietele/e90-c.4.758
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2007
AB - A DRAM-cell array with 12-F2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and read-out times of the twin-cell array are shorter than those of a single-cell array by 70% and 40% respectively, because of parallel writing and reading of half charge to and from two memory cells. According to measured retention characteristics of the single cells, the twin-cell array improves retention time by 20% compared with the single-cell array at 1 V and keeps the retention time of the single-cell array at 0.4 V. Furthermore, the cell accepts the plate-driven scheme without the need of a dummy cell, lowering the necessary word-line voltage by 0.4 V.
ER -
English
