We propose a Simulink model of a ring oscillator using saturating integrators. The oscillator's period is tuned via the saturation time of the integrators. Thus, timing jitters due to white and flicker noises are easily introduced into the model, enabling an efficient phase noise evaluation before transistor-level circuit design.
Zule XU
Tokyo University of Science
Takayuki KAWAHARA
Tokyo University of Science
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Zule XU, Takayuki KAWAHARA, "A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design" in IEICE TRANSACTIONS on Electronics,
vol. E100-C, no. 4, pp. 370-372, April 2017, doi: 10.1587/transele.E100.C.370.
Abstract: We propose a Simulink model of a ring oscillator using saturating integrators. The oscillator's period is tuned via the saturation time of the integrators. Thus, timing jitters due to white and flicker noises are easily introduced into the model, enabling an efficient phase noise evaluation before transistor-level circuit design.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E100.C.370/_p
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@ARTICLE{e100-c_4_370,
author={Zule XU, Takayuki KAWAHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design},
year={2017},
volume={E100-C},
number={4},
pages={370-372},
abstract={We propose a Simulink model of a ring oscillator using saturating integrators. The oscillator's period is tuned via the saturation time of the integrators. Thus, timing jitters due to white and flicker noises are easily introduced into the model, enabling an efficient phase noise evaluation before transistor-level circuit design.},
keywords={},
doi={10.1587/transele.E100.C.370},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 370
EP - 372
AU - Zule XU
AU - Takayuki KAWAHARA
PY - 2017
DO - 10.1587/transele.E100.C.370
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E100-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2017
AB - We propose a Simulink model of a ring oscillator using saturating integrators. The oscillator's period is tuned via the saturation time of the integrators. Thus, timing jitters due to white and flicker noises are easily introduced into the model, enabling an efficient phase noise evaluation before transistor-level circuit design.
ER -