We propose a Simulink model of a ring oscillator using saturating integrators. The oscillator's period is tuned via the saturation time of the integrators. Thus, timing jitters due to white and flicker noises are easily introduced into the model, enabling an efficient phase noise evaluation before transistor-level circuit design.

This paper describes an ADPLL (All Digital Phase-Locked Loops) with a small DCO (Digitally Controlled Oscillator), low jitter, fine resolution and wide lock range suitable for mobile appplications. The novel DCO circuit is controlled by digital control codes with thermometer type instead of previous binary weighted type. Therefore, the DCO has small area and it has significantly small jitter when the control input is updated. The hierarchical DCO type with two loops makes it possible to have fine resolution and wide lock range. Functional verification and noise analysis of the ADPLL is performed by MATLAB simulink to improve design TAT (Turn-Around Time). And The ADPLL chip is in fabrication using a SEC 0.18 µm CMOS technology. The ADPLL has lock range between 520 MHz and 1.5 GHz and has peak-to-peak jitter 70 ps at 670 MHz.

A non-data aided carrier recovery technique using digital modulation format identification called multi-mode PLL (Phase Locked Loop) is proposed. This technique can be interpreted as a modulation identification method that is robust against static phase and frequency offsets. The performance of the proposed technique is studied and the analytical expressions are derived for the probability of lock detection, acquisition time over AWGN channel in the cases of M-PSK and M-QAM modulations with respect to frequency offset and signal-to-noise ratio.

PSK coherent demodulation has difficulty in achieving high speed carrier extraction and symbol synchronization when implementing to slow FH-SS radio system. On the other hand, implementation to FPGA has the requirement of a small gate size to design because of FPGA cost issue. We developed a QPSK coherent demodulation digital modem for FH-SS radio systems using FPGA by solving problems. The designed modem performs symbol synchronization with no carrier extractions, under the limitation of the small gate size requirement. The modem employs shift arithmetic operation and a comb digital BPF to achieve very good synchronization lock-up performance with small gate size. In this paper, the symbol synchronization and the carrier tracking scheme are mainly discussed. Analysis of its performance and stability are also explained. The achievement of its very good performance is presented by experimental measurement.

Since most digital phase-locked loops (DPLLs) used in digital data transmission receivers require both fast acquisition of input frequency and phase in the beginning and substantial jitter reduction in the steady-state, the DPLL loop bandwidth is preferred to being adjusted accordingly. In this paper, a bandwidth adjusting (adaptive) algorithm is presented, which allow both fast acquisition and significant jitter reduction for each different noise environment and hardware requirement. This algorithm, based on the recursive least squares (RLS) criterion, suggest an optimal sequence of control parameters for a dual-loop DPLL which achieves the fastest initial acquisition time by trying to minimize the jitter variance in any given time instant. The algorithm can be used for carrier recovery or clock recovery in mobile communications, local area networks and disk drivers that require a short initial preamble period.