This paper presents an ultra-low power and temperature-independent voltage detector with a post-fabrication programming method, and presents a theoretical analysis and measurement results. The voltage detector is composed of a programmable voltage detector and a glitch-free voltage detector to realize both programmable and glitch-free operation. The programmable voltage detector enables the programmable detection voltages in the range from 0.52V to 0.85V in steps of less than 49mV. The glitch-free voltage detector enables glitch-free operation when the supply voltage is near 0V. A multiple voltage copier (MVC) in the programmable voltage detector is newly proposed to eliminate the tradeoff between the temperature dependence and power consumption. The design consideration and a theoretical analysis of the MVC are introduced to clarify the relationship between the current in the MVC and the accuracy of the duplication. From the analysis, the tradeoff between the duplication error and the current of MVC is introduced. The proposed voltage detector is fabricated in a 250nm CMOS process. The measurement results show that the power consumption is 248pW and the temperature coefficient is 0.11mV/°C.

This paper describes a logarithmic compression ADC using a subranging TDC and the transient response of a comparator. We utilized the settling time of the comparator for a logarithmic compression instead of a logarithmic amplifier. The settling time of the comparator is inversely proportional to the logarithm of an input voltage. In the proposed ADC, an input voltage is converted into a pulse whose width represents the settling time of the comparator. Subsequently, the TDC converts the pulse width into a binary code. The supply voltage of the proposed ADC can be reduced more than a conventional logarithmic ADC because an analog to digital conversion takes place in the time domain. We confirmed through a 0.18-µm CMOS circuit simulation that the proposed ADC achieves a resolution of 11 bits, a sampling rate of 20 MS/s, a dynamic range of 59 dB and a power consumption of 9.8 mW at 1.5 V operation.

A 1.9GHz film bulk acoustic resonator (FBAR)-based low-phase-noise complementary cross-coupled voltage-controlled oscillator (VCO) is presented. The FBAR-VCO is designed and fabricated in 0.18µm CMOS process. The DC latch and the low frequency instability are resolved by employing the NMOS source coupling capacitor and the DC blocked cross-coupled pairs. Since no additional voltage headroom is required, the proposed FBAR-VCO can be operated at a low power supply voltage of 1.1V with a wide voltage swing of 0.9V. An effective phase noise optimization is realized by a reasonable trade-off between the output resistance and the trans-conductance of the cross-coupled pairs. The measured performance shows the proposed FBAR-VCO achieves a phase noise of -148dBc/Hz at 1MHz offset with a figure of merit (FoM) of -211.6dB.

We propose a Simulink model of a ring oscillator using saturating integrators. The oscillator's period is tuned via the saturation time of the integrators. Thus, timing jitters due to white and flicker noises are easily introduced into the model, enabling an efficient phase noise evaluation before transistor-level circuit design.

In order to realize solid-state drives (SSDs) with high performance, low energy consumption and high reliability, storage class memory (SCM)/multi-level cell (MLC) NAND flash hybrid SSD has been proposed. Algorithm of the hybrid SSD should be designed according to SCM specifications and workload characteristics. In this paper, SCMs are used as non-volatile cache. Cache operation guidelines and optimal SCM specifications for the hybrid SSD are provided for various workload characteristics. Three kinds of non-volatile cache operation for the hybrid SSD are discussed: i) write cache, ii) read-write cache without space control (RW cache) and iii) read-write cache with space control (RW cache w/ SC). SSD workloads are categorized into eight according to read/write ratio, access frequency and access data size. From evaluation result, the write cache algorithm is suitable for write-intensive workloads and read-cold-sequential workloads, while the RW cache algorithm is suitable for read-cold-random workloads to achieve the highest performance of the hybrid SSD. In contrast, as for read-hot-random workloads, write cache is appropriate when the SCM capacity is less than 3% of the NAND flash capacity. On the other hand, RW cache should be used in case that SCM capacity is more than 5% of NAND flash capacity. The effect of Memory-type SCM (M-SCM) and Storage-type SCM (S-SCM) on the hybrid SSD performance is also analyzed. The M-SCM latency is below 1 us (high speed) but the capacity is only 2% of the NAND flash capacity (small capacity). On the other hand, the S-SCM capacity is assumed to be 5% of the NAND flash capacity (large capacity) but S-SCM speed is larger than 1 us (low speed). If the additional SCM cost is limited to 20% of MLC NAND flash cost, up to 7-times and 8-times performance improvement are achieved in write-hot-random workload and read-hot-random workloads, respectively. Moreover, if the additional SCM cost is the same as MLC NAND flash cost, M-SCM/MLC NAND flash hybrid SSD achieves 24-times performance improvement.

This paper presents a soft-error-tolerant memory-control circuit for SRAM-based field programmable gate arrays (FPGAs). A potential obstacle to applying such FPGAs to safety-critical industrial control systems is their low tolerance. The main reason is that soft errors damage circuit-configuration data stored in SRAM-based configuration memory. To overcome this obstacle, the soft-error tolerance must thus be improved while suppressing the circuit area overhead, and data stored in external memory must be protected when a fault occurs on the FPGA. Therefore, a memory-control circuit was developed on the basis of a dual-modular-redundancy (DMR) architecture. This memory controller has a repair and retry scheme that repairs damaged circuit-configuration data and re-executes unfinished accesses after the repair. The developed architecture reduces circuit redundancy below that of a commonly used triple-modular-redundancy (TMR) architecture. Moreover, a write-invalidation circuit was developed to protect data in external memory, and an external-memory-state recovery circuit was developed to enable resumption of memory access after fault repair. The developed memory controller was implemented in a prototype circuit on an FPGA and evaluated using the prototype. The evaluation results demonstrated that the developed memory controller can operate successfully for 1.03×10⁹ hours (at sea level). In addition, its circuit area overhead was found to be sufficiently smaller than that of the TMR architecture.

COordinate Rotation DIgital Computer (CORDIC) is an efficient algorithm to compute elementary arithmetic such as trigonometric, exponent, and logarithm. However, the main drawback of the conventional CORDIC is that the number of iterations is equal to the number of angle constants. Among a great deal of research to overcome this disadvantage, angle recording method is an effective method because it is capable of reducing 50% of the number of iterations. Nevertheless, the hardware architecture of this algorithm is difficult to implement in pipeline. Therefore, a low-latency parallel pipeline hybrid adaptive CORDIC (PP-CORDIC) architecture is proposed in this paper. In the design hybrid architecture was exploited together with pipeline and parallel technique to achieve low latency. This design is able to operate at 122.6 MHz frequency and costs 8, 12, and 15 clock cycles latency in the best, average, and worst case, respectively. More significantly, the latency of PP-CORDIC in the worst case is 1.1X lower than that of the Altera's commercial floating-point sine and cosine IP cores.

Nowadays, with the extensive use of smart devices, the amount of mobile data is experiencing an exponential growth. As a result, accommodating the large amount of traffic is important for the future 5G mobile communication. Millimeter-wave band, which has a lot of spectrum resources to meet the demand brought by the growth of mobile data, is becoming an important part of 5G technology. In order to mitigate the high path loss brought by the high frequency band, beamforming is often used to enhance the gain of a link. In this paper, we propose an iteration-based beamforming method for planar phased array. When compared to a linear array, a planar phased array points a smaller area which ensures a better link performance. We deduce that different paths of millimeter-wave channel are approximately orthogonal when the antenna array is large, which forms the basis of our iterative approach. We also discuss the development of the important millimeter-wave device-phase shifter, and its effect on the performance of the proposed beamforming method. From the simulation, we prove that our method has a performance close to the singular vector decomposition (SVD) method and is superior to the method in IEEE802.15.3c. Moreover, the channel capacity of the proposed method is at most 0.41bps/Hz less than the SVD method. We also show that the convergence of the proposed method could be achieved within 4 iterations and a 3-bit phase shifter is enough for practical implementation.

This paper presents a design optimization method for a Gm-C active filter via geometric programming (GP). We first describe a GP-compatible model of a cascaded Gm-C filter that forms a biquadratic output transfer function. The bias, gain, bandwidth, and signal-to-noise ratio (SNR) of the Gm-C filter are described in a GP-compatible way. To further enhance the accuracy of the model, two modeling techniques are introduced. The first, a two-step selection method, chooses whether a saturation or subthreshold model should be used for each transistor in the filter to enhance the modeling accuracy. The second, a bisection method, is applied to include non-posynomial inequalities in the filter modeling. The presented filter model is optimized via a GP solver along with proposed modeling techniques. The numerical experiments over wide ranges of design specifications show good agreement between model and simulation results, with the average error for gain, bandwidth, and SNR being less than 9.9%, 4.4%, and 14.6%, respectively.