IEICE TRANSACTIONS on Electronics
A Low-Latency Parallel Pipeline CORDIC
Summary :
COordinate Rotation DIgital Computer (CORDIC) is an efficient algorithm to compute elementary arithmetic such as trigonometric, exponent, and logarithm. However, the main drawback of the conventional CORDIC is that the number of iterations is equal to the number of angle constants. Among a great deal of research to overcome this disadvantage, angle recording method is an effective method because it is capable of reducing 50% of the number of iterations. Nevertheless, the hardware architecture of this algorithm is difficult to implement in pipeline. Therefore, a low-latency parallel pipeline hybrid adaptive CORDIC (PP-CORDIC) architecture is proposed in this paper. In the design hybrid architecture was exploited together with pipeline and parallel technique to achieve low latency. This design is able to operate at 122.6 MHz frequency and costs 8, 12, and 15 clock cycles latency in the best, average, and worst case, respectively. More significantly, the latency of PP-CORDIC in the worst case is 1.1X lower than that of the Altera's commercial floating-point sine and cosine IP cores.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E100-C No.4 pp.391-398
- Publication Date
- 2017/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E100.C.391
- Type of Manuscript
- Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
- Category
Authors
Hong-Thu NGUYEN
The University of Electro-Communications
Xuan-Thuan NGUYEN
The University of Electro-Communications
Cong-Kha PHAM
The University of Electro-Communications
Keyword
Latest Issue
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Hong-Thu NGUYEN, Xuan-Thuan NGUYEN, Cong-Kha PHAM, "A Low-Latency Parallel Pipeline CORDIC" in IEICE TRANSACTIONS on Electronics,
vol. E100-C, no. 4, pp. 391-398, April 2017, doi: 10.1587/transele.E100.C.391.
Abstract: COordinate Rotation DIgital Computer (CORDIC) is an efficient algorithm to compute elementary arithmetic such as trigonometric, exponent, and logarithm. However, the main drawback of the conventional CORDIC is that the number of iterations is equal to the number of angle constants. Among a great deal of research to overcome this disadvantage, angle recording method is an effective method because it is capable of reducing 50% of the number of iterations. Nevertheless, the hardware architecture of this algorithm is difficult to implement in pipeline. Therefore, a low-latency parallel pipeline hybrid adaptive CORDIC (PP-CORDIC) architecture is proposed in this paper. In the design hybrid architecture was exploited together with pipeline and parallel technique to achieve low latency. This design is able to operate at 122.6 MHz frequency and costs 8, 12, and 15 clock cycles latency in the best, average, and worst case, respectively. More significantly, the latency of PP-CORDIC in the worst case is 1.1X lower than that of the Altera's commercial floating-point sine and cosine IP cores.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E100.C.391/_p
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@ARTICLE{e100-c_4_391,
author={Hong-Thu NGUYEN, Xuan-Thuan NGUYEN, Cong-Kha PHAM, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Latency Parallel Pipeline CORDIC},
year={2017},
volume={E100-C},
number={4},
pages={391-398},
abstract={COordinate Rotation DIgital Computer (CORDIC) is an efficient algorithm to compute elementary arithmetic such as trigonometric, exponent, and logarithm. However, the main drawback of the conventional CORDIC is that the number of iterations is equal to the number of angle constants. Among a great deal of research to overcome this disadvantage, angle recording method is an effective method because it is capable of reducing 50% of the number of iterations. Nevertheless, the hardware architecture of this algorithm is difficult to implement in pipeline. Therefore, a low-latency parallel pipeline hybrid adaptive CORDIC (PP-CORDIC) architecture is proposed in this paper. In the design hybrid architecture was exploited together with pipeline and parallel technique to achieve low latency. This design is able to operate at 122.6 MHz frequency and costs 8, 12, and 15 clock cycles latency in the best, average, and worst case, respectively. More significantly, the latency of PP-CORDIC in the worst case is 1.1X lower than that of the Altera's commercial floating-point sine and cosine IP cores.},
keywords={},
doi={10.1587/transele.E100.C.391},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - A Low-Latency Parallel Pipeline CORDIC
T2 - IEICE TRANSACTIONS on Electronics
SP - 391
EP - 398
AU - Hong-Thu NGUYEN
AU - Xuan-Thuan NGUYEN
AU - Cong-Kha PHAM
PY - 2017
DO - 10.1587/transele.E100.C.391
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E100-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2017
AB - COordinate Rotation DIgital Computer (CORDIC) is an efficient algorithm to compute elementary arithmetic such as trigonometric, exponent, and logarithm. However, the main drawback of the conventional CORDIC is that the number of iterations is equal to the number of angle constants. Among a great deal of research to overcome this disadvantage, angle recording method is an effective method because it is capable of reducing 50% of the number of iterations. Nevertheless, the hardware architecture of this algorithm is difficult to implement in pipeline. Therefore, a low-latency parallel pipeline hybrid adaptive CORDIC (PP-CORDIC) architecture is proposed in this paper. In the design hybrid architecture was exploited together with pipeline and parallel technique to achieve low latency. This design is able to operate at 122.6 MHz frequency and costs 8, 12, and 15 clock cycles latency in the best, average, and worst case, respectively. More significantly, the latency of PP-CORDIC in the worst case is 1.1X lower than that of the Altera's commercial floating-point sine and cosine IP cores.
ER -
English
