In this paper, the hardware architecture of a CORDIC-based Arithmetic Processor utilizing both angle recoding (ARD) CORDIC algorithm and scaling-free (SCFE) CORDIC algorithm is proposed and implemented in 180 nm CMOS technology. The arithmetic processor is capable of calculating the sine, cosine, sine hyperbolic, cosine hyperbolic, and multiplication function. The experimental results prove that the design is able to work at 100 MHz frequency and requires 12.96 mW power consumption. In comparison with some previous work, the design can be seen as a good choice for high-throughput low-energy applications.

COordinate Rotation DIgital Computer (CORDIC) is an efficient algorithm to compute elementary arithmetic such as trigonometric, exponent, and logarithm. However, the main drawback of the conventional CORDIC is that the number of iterations is equal to the number of angle constants. Among a great deal of research to overcome this disadvantage, angle recording method is an effective method because it is capable of reducing 50% of the number of iterations. Nevertheless, the hardware architecture of this algorithm is difficult to implement in pipeline. Therefore, a low-latency parallel pipeline hybrid adaptive CORDIC (PP-CORDIC) architecture is proposed in this paper. In the design hybrid architecture was exploited together with pipeline and parallel technique to achieve low latency. This design is able to operate at 122.6 MHz frequency and costs 8, 12, and 15 clock cycles latency in the best, average, and worst case, respectively. More significantly, the latency of PP-CORDIC in the worst case is 1.1X lower than that of the Altera's commercial floating-point sine and cosine IP cores.