Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA
Summary :
This paper presents a soft-error-tolerant memory-control circuit for SRAM-based field programmable gate arrays (FPGAs). A potential obstacle to applying such FPGAs to safety-critical industrial control systems is their low tolerance. The main reason is that soft errors damage circuit-configuration data stored in SRAM-based configuration memory. To overcome this obstacle, the soft-error tolerance must thus be improved while suppressing the circuit area overhead, and data stored in external memory must be protected when a fault occurs on the FPGA. Therefore, a memory-control circuit was developed on the basis of a dual-modular-redundancy (DMR) architecture. This memory controller has a repair and retry scheme that repairs damaged circuit-configuration data and re-executes unfinished accesses after the repair. The developed architecture reduces circuit redundancy below that of a commonly used triple-modular-redundancy (TMR) architecture. Moreover, a write-invalidation circuit was developed to protect data in external memory, and an external-memory-state recovery circuit was developed to enable resumption of memory access after fault repair. The developed memory controller was implemented in a prototype circuit on an FPGA and evaluated using the prototype. The evaluation results demonstrated that the developed memory controller can operate successfully for 1.03×109 hours (at sea level). In addition, its circuit area overhead was found to be sufficiently smaller than that of the TMR architecture.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E100-C No.4 pp.382-390
- Publication Date
- 2017/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E100.C.382
- Type of Manuscript
- Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
- Category
Authors
Makoto SAEN
Hitachi, Ltd.
Tadanobu TOBA
Hitachi, Ltd.
Yusuke KANNO
Hitachi, Ltd.
Keyword
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Makoto SAEN, Tadanobu TOBA, Yusuke KANNO, "Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA" in IEICE TRANSACTIONS on Electronics,
vol. E100-C, no. 4, pp. 382-390, April 2017, doi: 10.1587/transele.E100.C.382.
Abstract: This paper presents a soft-error-tolerant memory-control circuit for SRAM-based field programmable gate arrays (FPGAs). A potential obstacle to applying such FPGAs to safety-critical industrial control systems is their low tolerance. The main reason is that soft errors damage circuit-configuration data stored in SRAM-based configuration memory. To overcome this obstacle, the soft-error tolerance must thus be improved while suppressing the circuit area overhead, and data stored in external memory must be protected when a fault occurs on the FPGA. Therefore, a memory-control circuit was developed on the basis of a dual-modular-redundancy (DMR) architecture. This memory controller has a repair and retry scheme that repairs damaged circuit-configuration data and re-executes unfinished accesses after the repair. The developed architecture reduces circuit redundancy below that of a commonly used triple-modular-redundancy (TMR) architecture. Moreover, a write-invalidation circuit was developed to protect data in external memory, and an external-memory-state recovery circuit was developed to enable resumption of memory access after fault repair. The developed memory controller was implemented in a prototype circuit on an FPGA and evaluated using the prototype. The evaluation results demonstrated that the developed memory controller can operate successfully for 1.03×109 hours (at sea level). In addition, its circuit area overhead was found to be sufficiently smaller than that of the TMR architecture.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E100.C.382/_p
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@ARTICLE{e100-c_4_382,
author={Makoto SAEN, Tadanobu TOBA, Yusuke KANNO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA},
year={2017},
volume={E100-C},
number={4},
pages={382-390},
abstract={This paper presents a soft-error-tolerant memory-control circuit for SRAM-based field programmable gate arrays (FPGAs). A potential obstacle to applying such FPGAs to safety-critical industrial control systems is their low tolerance. The main reason is that soft errors damage circuit-configuration data stored in SRAM-based configuration memory. To overcome this obstacle, the soft-error tolerance must thus be improved while suppressing the circuit area overhead, and data stored in external memory must be protected when a fault occurs on the FPGA. Therefore, a memory-control circuit was developed on the basis of a dual-modular-redundancy (DMR) architecture. This memory controller has a repair and retry scheme that repairs damaged circuit-configuration data and re-executes unfinished accesses after the repair. The developed architecture reduces circuit redundancy below that of a commonly used triple-modular-redundancy (TMR) architecture. Moreover, a write-invalidation circuit was developed to protect data in external memory, and an external-memory-state recovery circuit was developed to enable resumption of memory access after fault repair. The developed memory controller was implemented in a prototype circuit on an FPGA and evaluated using the prototype. The evaluation results demonstrated that the developed memory controller can operate successfully for 1.03×109 hours (at sea level). In addition, its circuit area overhead was found to be sufficiently smaller than that of the TMR architecture.},
keywords={},
doi={10.1587/transele.E100.C.382},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA
T2 - IEICE TRANSACTIONS on Electronics
SP - 382
EP - 390
AU - Makoto SAEN
AU - Tadanobu TOBA
AU - Yusuke KANNO
PY - 2017
DO - 10.1587/transele.E100.C.382
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E100-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2017
AB - This paper presents a soft-error-tolerant memory-control circuit for SRAM-based field programmable gate arrays (FPGAs). A potential obstacle to applying such FPGAs to safety-critical industrial control systems is their low tolerance. The main reason is that soft errors damage circuit-configuration data stored in SRAM-based configuration memory. To overcome this obstacle, the soft-error tolerance must thus be improved while suppressing the circuit area overhead, and data stored in external memory must be protected when a fault occurs on the FPGA. Therefore, a memory-control circuit was developed on the basis of a dual-modular-redundancy (DMR) architecture. This memory controller has a repair and retry scheme that repairs damaged circuit-configuration data and re-executes unfinished accesses after the repair. The developed architecture reduces circuit redundancy below that of a commonly used triple-modular-redundancy (TMR) architecture. Moreover, a write-invalidation circuit was developed to protect data in external memory, and an external-memory-state recovery circuit was developed to enable resumption of memory access after fault repair. The developed memory controller was implemented in a prototype circuit on an FPGA and evaluated using the prototype. The evaluation results demonstrated that the developed memory controller can operate successfully for 1.03×109 hours (at sea level). In addition, its circuit area overhead was found to be sufficiently smaller than that of the TMR architecture.
ER -
English
