This paper proposes a new associative memory architecture using stochastic behavior in single electron tunneling (SET) devices. This memory stochastically extracts the pattern most similar to the input key pattern from the stored patterns in two matching modes: the voltage-domain matching mode and the time-domain one. In the former matching mode, ordinary associative memory operation can be performed. In the latter matching mode, a purely stochastic search can be performed. Even in this case, by repeating numerous searching trials, the order of similarity can be obtained. We propose a circuit using SET devices based on this architecture and demonstrate its basic operation with a simulation. By feeding the output pattern back to the input, this memory retrieves slightly dissimilar patterns consecutively. This function may be the key to developing highly intelligent information processing systems close to the human brain.

This paper presents a soft-error-tolerant memory-control circuit for SRAM-based field programmable gate arrays (FPGAs). A potential obstacle to applying such FPGAs to safety-critical industrial control systems is their low tolerance. The main reason is that soft errors damage circuit-configuration data stored in SRAM-based configuration memory. To overcome this obstacle, the soft-error tolerance must thus be improved while suppressing the circuit area overhead, and data stored in external memory must be protected when a fault occurs on the FPGA. Therefore, a memory-control circuit was developed on the basis of a dual-modular-redundancy (DMR) architecture. This memory controller has a repair and retry scheme that repairs damaged circuit-configuration data and re-executes unfinished accesses after the repair. The developed architecture reduces circuit redundancy below that of a commonly used triple-modular-redundancy (TMR) architecture. Moreover, a write-invalidation circuit was developed to protect data in external memory, and an external-memory-state recovery circuit was developed to enable resumption of memory access after fault repair. The developed memory controller was implemented in a prototype circuit on an FPGA and evaluated using the prototype. The evaluation results demonstrated that the developed memory controller can operate successfully for 1.03×109 hours (at sea level). In addition, its circuit area overhead was found to be sufficiently smaller than that of the TMR architecture.